• Progress in Superconductivity
• /
• v.4 no.2
• /
• pp.127-131
• /
• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Journal of Sensor Science and Technology
• /
• v.33 no.3
• /
• pp.134-138
• /
• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Journal of Korea Society of Industrial Information Systems
• /
• v.19 no.6
• /
• pp.33-41
• /
• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.1
• /
• pp.10-14
• /
• 1998

In this paper a double edge triggered (DET) filp-flop is proposed which changes its output state at both the positive and the negative edge transitions of the triggering input. DET filp-flop has advantages in terms of speed and power dissipation over single edge triggered (SET) filp-flop has proposed DET flip-flop needs only 12 MOS transistors and can operate at clock speed of 500 MHz. Also, the power dissipation has decreased about 33% in comparison to SET flip-flop.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.12
• /
• pp.1055-1061
• /
• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.

• Progress in Superconductivity and Cryogenics
• /
• v.4 no.1
• /
• pp.35-39
• /
• 2002

We have simulated and laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. SFQ AND gate circuit is a combination of two D Flip-Flop. D Flip-Flop and dc SQUID are the similar shape form the fact that it has the loop inductor and two Josephson junction We obtained perating margins and accomplished layout of the AND gate. We got the margin of $\pm$38%. over. After layout, we drew mask for fabrication of SFQ AND sate. This mask was included AND gate, dcsfq, sfqdc, rs flip-flop and jtl.

• 전자공학회논문지 IE
• /
• v.44 no.2
• /
• pp.14-20
• /
• 2007

This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.697-699
• /
• 2017

A novel structure of phase locked loop (PLL) which has small size with D Flip-Flop and sub charge pump has been proposed. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.7
• /
• pp.75-81
• /
• 1993

In this paper, New type of Static Edge Triggered D Flip-Flop Circuits which are effective for the sequencial selecting and addressing of Matrix type Electrodes being applied to Flat Display Devices is proposed by the Design Technique using the Transmission Characteristics of Feedback Transistors and Charge Back Up Function. These Circuits composed of 2-4 less transistors in number than Conventional Static D Flip Flop's have some advantages that the Maximum Transition Time of Clock Signals allowed is increased by 100-450 times more than that of the Conventional circuit at 100KHz Clock Frequence and Circuit Safety is much increased by making the wider ranges, 1-4V, of Clock Levelas a Non-operating periods than 3-3.2V ranges in case of the Conventional Circuit at 10MHz clock frequence. By these advantages, These circuits can be very effectively used in case that clock signal has long transition time, especially on the low frequency operation.

• Journal of the Optical Society of Korea
• /
• v.14 no.2
• /
• pp.137-141
• /
• 2010

We report, for the first time to our knowledge, observation of polarization bistability from 1.55-${\mu}m$ wavelength single-mode VCSELs of a conventional cylinder-shape under control of their driving current, and demonstration of all-optical flip-flop (AOFF) operations based on the bistability with optical set and reset pulse injection at a 50 MHz switching frequency. The injection pulse energy was less than 14 fJ. The average on-off contrast ratio of the flip-flopped signals was about 7 dB. These properties of the VCSELs will be potentially useful for future high-speed all-optical signal processing applications.