• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• Journal of Information Display
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• v.9 no.3
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• pp.1-7
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• 2008

With the aim of creating a high-quality display system with value-added functions, we designed a current mode multiplexer for LTPS TFT devices. The multiplexers had less than 1 volt logic swing, and speed improvement was evident compared with that of conventional CMOS architecture. We refined the multiplexer to achieve a more stable current steering operation. By using the versatility of the multiplexer, a new NAND/AND and NOR/OR logic gates were designed through the simple modification of signal connections. Two micron LTPS TFT parameters were used during the HSPICE simulation of the circuits.

• Journal of Advanced Marine Engineering and Technology
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• v.21 no.4
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• pp.387-392
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• 1997

This paper describes a combination surge generator for carrying out performance tests on the surge protection circuits of shipboard electrical systems. Pspice simulations were performed to decide the values of the parts required and to analyze the characteristics of the generator circuitry. The surge generator fabricated can produce four of the most common surge test waveforms : the O.5i/S/100kHz Ringwave, the 1.2/50$\mu$S voltage, the 8/20$\mu$S current, and the lO/lOOOi/S voltage wave¬forms specified in ANSI Std. C62. Source impedances of the surge generator are 12$\Omega$ in the O.5$\mu$S/100kHz mode, O.5$\Omega$ in the 1.2/50$\mu$S and 8/20$\mu$S mode, and 40$\Omega$in the l0/1000$\mu$S mode, and are determined by the ratio of the maxi¬mum open - circuit voltage to the maximum short - circuit current. Experimental results show that the surge generator provides most of the outputs required for the testing of the surge protection circuits on shipboard electrical systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3614-3621
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• 2009

In this paper, A CMOS low-voltage current mode integrator is designed. The designed current-mode integrator is based on linear cascode circuit that is newly proposed in this paper. When it is compared with gain(43.7dB) and unity gain frequency(15.2MHz) of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain(47.8dB) and unity gain frequency(27.8MHz). And a 5th Chebyshev current-mode filter with 7.03MHz cutoff frequency is designed. The designed all circuits are simulated by HSPICE using 1.8V-$0.18{\mu}m$ CMOS technology.

• International Journal of Aerospace System Engineering
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• v.9 no.1
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• pp.1-15
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• 2022

Pyrotechnic initiators provide a source of pyrotechnic energy used to initiate a variety of space mechanisms. Pyrotechnic systems build in electromagnetic environment that may lead to critical or catastrophic hazards. Special precautions are need to prevent a pulse large enough to trigger the initiator from appearing in the pyrotechnic firing circuits at any but the desired time. The EMC verification shall be shown by analysis or test that the pyrotechnic systems meets the requirements of inadvertent activation. The MIL-STD-1576 and two range safeties, AFSPC and CSG, require the safety margin for electromagnetic potential hazards to pyrotechnic systems to a level at least 20 dB below the maximum no-fire power of the EED. The PC23 is equivalent to NASA standard initiator and the 1EPWH100 squib is ESA standard initiator. This paper verifies the two safety margins for electromagnetic potential hazards. The first is verified by analyzing against a RF power. The second is verified by testing against a DC current. The EMC safety margin requirement against RF power has been demonstrated through the electric field coupling analysis in differential mode with 21 dB both PC23 and 1EPWH100, and in common mode with 58 dB for PC23 and 48 dB for 1EPWH100 against the maximum no-fire power of the EED. Also, the EMC safety margin requirement against DC current has been demonstrated through the electrical isolation test for the pyrotechnic firing circuits with greater than 20 dB below the maximum no-fire current of the EED.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1068-1076
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analyog current-mode active filters is proposed. Compared to the current-mode integrator which is proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter is designed with the proposed current-mode integrator. The designed circuits are fabricated using the ORBIT's $1.2{\mu}{\textrm{m}}$ deouble-poly double-metal CMOS n-well process. The experimental results show that the filter has -3dB cutoff frequency at 44.5MHz and 3mW power dissipation with single 3.3V power supply and also $0.12mm^{2}$ chip area.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.