• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.411-414
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• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.

• Journal of Electrical Engineering and Technology
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• v.5 no.1
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• pp.171-178
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• 2010

Resonant parametric perturbation (RPP) method is an effective non-feedback method for controlling chaos. In this paper, the above method is applied for the current programmed buck-boost dc-dc converter which exhibits chaotic for wide parameter variations. The different possible operating regimes leading to chaotic operation of the current mode controlled buck-boost converter is discussed and the control of chaos by RPP method is demonstrated through computer simulations and experimental studies. The converter is stabilized to period 1 operation practically.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.531-537
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• 2018

This paper propose a bidirectional dc-to-dc converter employing dual inductor for current ripple reduction. Conventional bidirectional dc-to-dc converter uses a single inductor for two different modes; boost and buck; therefore it is difficult to satisfy the optimized inductance value for each mode. To improve this problem, the proposed converter adds two switches, a diode, and one inductor. By proper switching of the additional switch, the proposed converter operates with a inductor in boost mode, but it works with dual inductor in buck mode. Hence in both modes the proposed bidirectional converter can be operated with optimized inductance values. Most of all the optimized inductance in buck mode can reduce the current ripple and its effective value(rms), which are directly related to the temperature increase resulted in short lifetime of battery. To verify the validity of the proposed approach, we first analyzes the operation of the proposed converter theoretically, and implement computer-aided simulations and experiments using a prototype.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.24-31
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• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.6
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• pp.25-32
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• 2011

This paper proposes high efficiency current-mode DC-DC buck converter that are suitable for portable devices. The current-mode DC-DC buck converter using adjustable Dead-time control method improves the power efficiency 2~5%. The buck converter has been implemented with a standard 0.35${\mu}m$ CMOS process. The size of this chip is 0.97$mm^2$. The input range of the fabricated DC-DC buck converter is 2.5V~3.3V, and the output is 1.8V. The maximum loading current of the converter is 500mA and the peak efficiency is 93% at 200mA loads.

• Journal of Power Electronics
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• v.7 no.4
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• pp.318-327
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• 2007

The design and performance analysis of a power factor corrected (PFC), single-phase, single switch flyback buck-boost ac-dc converter is carried out for low power battery charging applications. The proposed configuration of the flyback buck-boost ac-dc converter consists of only one switch and operates in discontinuous current mode (DCM), resulting in simplicity in design and manufacturing and reduction in input current total harmonic distortion (THD). The design procedure of the flyback buck-boost ac-dc converter is presented for the battery charging application. To verify and investigate the design and performance, a simulation study of the flyback buck-boost converter in DCM is performed using the PSIM6.0 platform. A laboratory prototype of the proposed single switch flyback buck-boost ac-dc converter is developed and test results are presented to validate the design and developed model of the system.

• Journal of IKEEE
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• v.15 no.2
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• pp.134-142
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• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.