• 전자공학회논문지B
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• 제33B권4호
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• pp.52-62
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analog current-mode active filters was proposed. Compared to the current-mode integrator which was proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter was designed with the proposed current-mode integrator. The designed circuits were fabricated using the ORBIT's 1.2.mu.m double-poly double-metal CMOS n-well process. The experimental resutls of the active filter designed and fabricated for this research have shown that it has the performance of 44.5MHz cutoff frequency, 3.3mW power dissipation and the third-order active filter area was 0.12mm$^{2}$.

• 한국통신학회논문지
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• 제21권7호
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• pp.1726-1733
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• 1996

A 3V-50MHz analog CMOS continuous-time current-mode filter with a negative resistance load(NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. the inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5.mu.m CMOS n-well proess. Simulation result shows the cutoff frequency of 50MHz and power consumption of 2.4mW/pole with a 3V power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.155-158
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• 2000

Circuit configurations for realizing of biquadratic current transfer functions using current conveyors (CCIIs) are presented. The circuits are composed of three multiple-output CCIIs and four passive elements (two resistors and two grounded capacitors), and when current controlled conveyors (CCIIs) in place of CCIIs are employed, the circuit can be realized using three multiple-output CCIIs and two grounded capacitors. Use of grounded capacitors is suitable for integrated implementation. The cutoff frequency of a realized filter with current gain K can be tuned independently of Q by the value of K.

• 대한전자공학회논문지TC
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• 제48권11호
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• pp.89-94
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• 2011

본 논문에서는 밀리미터파 Tuner system을 이용하여 밀리미터파 탐색기에 적용 가능한 W-band MMIC 저잡음 증폭기를 구현하였다. 저잡음 증폭기를 위해 구현된 MHEMT의 측정결과 692mA/mm의 드레인 전류 밀도, 726mS/mm의 최대전달컨덕턴스를 얻었으며, RF 특성으로 전류이득차단주파수는 195GHz, 최대공진주파수는 305GHz의 양호한 성능을 나타내었다. 제작된 W-band 저잡음 증폭기의 측정결과 94GHz에서 7.42dB의 우수한 S21 이득 특성을 얻었으며, 잡음 지수의 측정결과 94.2GHz에서 2.8dB의 잡음 특성을 얻었다.

• 한국전기전자재료학회논문지
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• 제11권5호
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• pp.365-370
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• 1998

We studied a electrical properties in GaAs/AlGaAs/InGaAs pseudomorphic high electron mobility transistors(PHEMT s) recessed by electron cyclotron resonance(ECR) plasma and wet etching. Using the $NH_4OH$ solution, a nonvolatile AlF$_3$layer formed on AlGaAs surface after selective gate recess is effectively eliminated. Also, we controlled threshold voltage($V_th$) using $H_3PO_4$ etchant. We have fabricated a device with 540 mS/mm maximum transconductance and -0.2 V threshold voltage by using $NH_4OH$ and $H_3PO_4$dip after ECR gate recessing. In a 2-finger GaAs PHEMT with a gate length of 0.2$\mu m$ and width of 100 $\mu m$, a current gain of 15 dB at 10 GHz and a maximum cutoff frequency of 58.9 GHz have been obtained from the measurement of current gain as a function of frequency at 12mA $I_{dss}$ and 2 V souce-drain voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.623-624
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• 2006

In this paper, we introduce the design and fabrication of V-band power amplifier MMIC with excellent gain-flatness for IEEE 802.15.3c WPAN system. The V-band power amplifier was designed using ETRI' $0.12{\mu}m$ PHEMT process. The PHEMT shows a peak transconductance ($G_{m,peak}$) of 500 mS/mm, a threshold voltage of -1.2 V, and a drain saturation current of 49 mA for 2 fingers and $100{\mu}m$ total gate width (2f100) at $V_{ds}$=2 V. The RF characteristics of the PHEMT show a cutoff frequency, $f_T$, of 97 GHz, and a maximum oscillation frequency, $f_{max}$, of 166 GHz. The gains of the each stages of the amplifier were modified to have broadband characteristics of input/output matching for first and fourth stages and get more gains of edge regions of operating frequency range for second and third stages in order to make the gain-flatness of the amplifier excellently for wide band. The performances of the fabricated 60 GHz power amplifier MMIC are operating frequency of $56.25{\sim}62.25\;GHz$, bandwidth of 6 GHz, small signal gain ($S_{21}$) of $16.5{\sim}17.2\;dB$, gain flatness of 0.7 dB, an input reflection coefficient ($S_{11}$) of $-16{\sim}-9\;dB$, output reflection coefficient ($S_{22}$) of $-16{\sim}-4\;dB$ and output power ($P_{out}$) of 13 dBm. The chip size of the amplifier MMIC was $3.7{\times}1.4mm^2$.

• 전자공학회논문지A
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• 제30A권12호
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• pp.51-59
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• 1993

A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.583-584
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• 2006

This paper presents transistor matching in 70 nm nMOS. To adopt radio frequency(RF) applications, the RF performance, especially the current gain cutoff frequency($f_T$), is examined experimentally through a wafer. It is proved that the RF performance variation of 70 nm nMOS is dependent to the device geometry, the total width(W). The RF performance variation of 70 nm nMOS is inversely proportional to square root of total width(W). Also, decreasing of the number of fingers($N_f$) is helpful to decrease the variation of 70 nm nMOS.

• 한국자동차공학회논문집
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• 제22권6호
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• pp.23-30
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• 2014

This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.