• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.99-106
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• 2012

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.92-97
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• 2006

In this paper, a fully integrated Ku-band tripler differential MMIC voltage controlled oscillator(VCO), which consists of a differential VCO core and two triplers, is developed using high linearity InGaP/GaAs HBT technology. The VCO core generates an oscillation frequency of 3.583 GHz, an output power of 3.65 dBm, and a phase noise of -96.7 dBc/Hz at 100 kHz offset with a current consumption of 30 mA at a supply voltage of 2.9 V. The tripler shows excellent side band rejection of 23 dBc at 3 V and 12 mA. The tripler differential MMIC VCO produces an oscillation frequency of 10.75 GHz, an output power of -13 dBm and a phase noise of -89.35 dBc/Hz at 100 kHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.506-510
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• 2016

A triple-band (TB) oscillator was implemented in the TSMC $0.18{\mu}m$ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt $4^{th}$ order LC resonators to form a $6^{th}$ order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 GHz, 5.82-6.15 GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is $0.835{\times}1.103mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.89-96
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gain control are proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0㎃ to 300㎃ over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than 1.4% over the current range from 0A to 300㎃.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.1
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• pp.40-44
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• 2014

A bridge resistance deviation-to-period (BRD-to-P) converter is presented for interfacing resistive biosensors. It consists of a linear operational transconductance amplifier (OTA) and a current-controlled oscillator (CCO) formed by a current-tunable Schmitt trigger and an integrator. The free running period of the converter is 1.824 ms when the bridge offset resistance is $1k{\Omega}$. The conversion sensitivity of the converter amounts to $3.814ms/{\Omega}$ over the resistance deviation range of $0-1.2{\Omega}$. The linearity error of the conversion characteristic is less than ${\pm}0.004%$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.