• 대한청각학회지
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• 제24권3호
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• pp.119-126
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• 2020

Background and Objectives: In distracting listening conditions, individuals need to pay extra attention to selectively listen to the target sounds. To investigate the amount of listening effort required in reverberating and noisy backgrounds, a semantic mismatch was examined. Subjects and Methods: Electroencephalography was performed in 18 voluntary healthy participants using a 64-channel system to obtain N400 latencies. They were asked to listen to sounds and see letters in 2 reverberated×2 noisy paradigms (i.e., Q-0 ms, Q-2000 ms, 3 dB-0 ms, and 3 dB-2000 ms). With auditory-visual pairings, the participants were required to answer whether the auditory primes and letter targets did or did not match. Results: Q-0 ms revealed the shortest N400 latency, whereas the latency was significantly increased at 3 dB-2000 ms. Further, Q-2000 ms showed approximately a 47 ms delayed latency compared to 3 dB-0 ms. Interestingly, the presence of reverberation significantly increased N400 latencies. Under the distracting conditions, both noise and reverberation involved stronger frontal activation. Conclusions: The current distracting listening conditions could interrupt the semantic mismatch processing in the brain. The presence of reverberation, specifically a 2000 ms delay, necessitates additional mental effort, as evidenced in the delayed N400 latency and the involvement of the frontal sources in this study.

• Journal of Audiology & Otology
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• 제24권3호
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• pp.119-126
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• 2020

Background and Objectives: In distracting listening conditions, individuals need to pay extra attention to selectively listen to the target sounds. To investigate the amount of listening effort required in reverberating and noisy backgrounds, a semantic mismatch was examined. Subjects and Methods: Electroencephalography was performed in 18 voluntary healthy participants using a 64-channel system to obtain N400 latencies. They were asked to listen to sounds and see letters in 2 reverberated×2 noisy paradigms (i.e., Q-0 ms, Q-2000 ms, 3 dB-0 ms, and 3 dB-2000 ms). With auditory-visual pairings, the participants were required to answer whether the auditory primes and letter targets did or did not match. Results: Q-0 ms revealed the shortest N400 latency, whereas the latency was significantly increased at 3 dB-2000 ms. Further, Q-2000 ms showed approximately a 47 ms delayed latency compared to 3 dB-0 ms. Interestingly, the presence of reverberation significantly increased N400 latencies. Under the distracting conditions, both noise and reverberation involved stronger frontal activation. Conclusions: The current distracting listening conditions could interrupt the semantic mismatch processing in the brain. The presence of reverberation, specifically a 2000 ms delay, necessitates additional mental effort, as evidenced in the delayed N400 latency and the involvement of the frontal sources in this study.

• 한국전자통신학회논문지
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• 제8권3호
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• pp.471-477
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• 2013

본 논문에서는 하이브리드 궤도회로를 이용한 정위치 정차시스템에 대한 가능성에 대해 연구하였다. 하이브리드 궤도회로는 UHF대역의 RFID시스템을 이용하고 실시간 운영체제를 기반으로 철도차상시스템과의 통신이 가능한 차세대 철도신호시스템의 한 부분이다. 본 논문에서 사용된 UHF대역 RFID 시스템은 원형편파의 태그와 리더 안테나가 사용되고 일체형 리더기는 송신출력 25dBm에서 우수한 인식회수를 얻었다. 현재 수동운행중인 지하철 차량에 이 시스템을 적용하여 정위치 정차를 하게 되면 기존 수동운전에서 기관사의 실수로 역을 지나거나 PSD(Platform Screen Door)와 열차출입문이 Mismatch 되는 현상을 방지할 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.737-739
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• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권12호
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• Journal of Power Electronics
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• 제17권5호
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• pp.1327-1337
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• 2017

Photovoltaic (PV) systems are influenced by disproportionate impacts on energy production caused by frequent mismatch cases. The occurrence of multiple maximum power points (MPPs) adds complexity to the tracking process in various PV systems. However, current maximum-power point tracking (MPPT) techniques exhibit limited performance. This paper introduces an enhanced simulated annealing (ESA)-based GMPPT technique against multiple MPP issues in P-V curve with different PV system structures. The proposed technique not only distinguishes global and local MPPs but also performs rapid convergence speed and high tracking accuracy of irradiance changing and restart capability detection. Moreover, the proposed global maximum power tracking algorithm can be applied in the central converter of DMPPT and hybrid PV system to meet various application scenarios. Its effectiveness is verified by simulation and test results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.47-50
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• 2000

This paper investigated structural and electrical properties of $Y_2$ $O_3$ as a buffer layer of single transistor FRAM (ferroelectric RAM). $Y_2$ $O_3$ buffer layers were deposited at a low substrate temperature below 40$0^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post-annealing temperature, and suppression of interfacial $SiO_2$ layer generation. For a well-fabricated sample, we achieved that leakage current density ( $J_{leak}$) in the order of 10$^{-7}$ A/$\textrm{cm}^2$, breakdown electric field ( $E_{br}$ ) about 2 MV/cm for $Y_2$ $O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_2$ $O_3$/Si as low as 8.72x1010 c $m^{-2}$ e $V^{-1}$ . The low interface states were obtained from very low lattice mismatch less than 1.75%.

• Journal of Digestive Cancer Research
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• 제10권2호
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• pp.65-73
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• 2022

A breakthrough in immunotherapy has changed the outlook for metastatic colorectal cancer (mCRC) treatment as the immune surveillance evasion mechanism of tumor cells has been continuously elucidated. Immune checkpoint inhibitors (ICI), such as pembrolizumab, nivolumab, and ipilimumab, which block immune checkpoint receptors or ligands have been approved for the treatment of mismatch repair deficient (dMMR)/microsatellite instability-high (MSI-H) mCRC based on numerous clinical studies. However, 50% of dMMR/MSI-H mCRC and most mismatch repair proficient/microsatellite stable mCRC remained unresponsive to current immunotherapy. Clinical trials on combination therapy that adds various treatments, such as target agents, chemotherapy, or radiation therapy to ICI, have been actively conducted to overcome this immunotherapy limitation. Further studies on safety and efficacy are needed although several trials presented promising data. Additionally, dMMR/MSI-H, tumor mutation burden, and programmed cell death ligand-1 expression have been studied as biomarkers for predicting the treatment response to immunotherapy, but the discovery and validation of more sensitively predictable biomarkers remained necessary. Thus, this study aimed to review recent studies on immunotherapy in mCRC, summarize the efficacy and limitation of immunotherapy, and describe the biomarkers that predict treatment response.

• 전자공학회논문지
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• 제51권11호
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• pp.94-100
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• 2014

본 논문에서는 전류-재사용 구조를 사용하여 1.95 GHz~3.15 GHz 의 광범위한 튜닝 범위를 갖는 저전력 전압 제어 발진기(VCO)를 설계하였다. 클래스-C 타입을 적용하여 위상 잡음 특성을 향상 시켰으며, 2 단계 자동 진폭 캘리브레이션 기법을 통해 전류-재사용 전압제어발진기 구조의 가장 큰 단점인 차동 출력 전압간의 불균형을 최소화 하였다. 차동 출력 전압간의 차이는 1.5mV ~ 4.5mV 가량으로 나타나며, 이는 출력 전압의 0.6% 이내 오차이다. 제안하는 전류-재사용 전압제어발진기는 CMOS $0.13{\mu}m$ 공정을 사용하여 설계 하였다. 공급 전압은 1.2 V를 사용하였고, 소모 전류는 2.3 GHz에서 2.6 mA이다. 출력주파수가 2.3 GHz에서 위상 잡음은 -116.267 dBc/Hz(@1MHz Offset)이며, 레이아웃 면적은 $720{\times}580{\mu}m^2$ 이다.