• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.442-445
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• 2003

In this study, we developed the 40 J-class MPC(magnetic pulse compression) system for exciting excimer laser and investigated the optimal conditions of each stage of MPC circuit. This system consists of a DC power supply, a pulse transformer and four saturable inductors. The number of turns of saturable inductors at each stage of MPC circuit are 140, 25, 5, 1 and the optimal storage capacitance of each stage are 34 nF, 28.9 nF, 22.1 nF, respectively. In the improvement MPC system, we have obtained an output voltage of 43 kV, a current of 8.25 kA and a pulse duration of 360 ns. Also, the maximum pulse compression ratio of 77.7 and the current gain of 71.7 were obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• The Journal of the Convergence on Culture Technology
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• v.6 no.4
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• pp.727-732
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• 2020

In this paper, when a refractive index grating and a gain grating were simultaneously present in a DFB laser having a wavelength of 1.55 ㎛, a dielectric film coating was applied so that reflection did not occur on the right mirror surface, so that 𝜌_r=0. In case of δL > 0, the threshold gain and the beam distribution in the longitudinal direction and the radiated power ratio P_l/P_r of the oscillation mode were compared for the cases of the phase of 𝜌_l=π and π/2. If the phase of 𝜌_l=π, in order to obtain a low threshold current and high frequency stability, κL should be greater than 8. In the case of the phase of 𝜌_l= π/2, when κL is larger than 4.0, the oscillation gain starts to be lower than when the phase of 𝜌_l=π. In order to lower the threshold current of a oscillation mode and enhance the frequency stability, κL should be greater than 8.

• Journal of the Korean Vacuum Society
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• v.14 no.4
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• pp.229-237
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• 2005

The degradation phenomena in SiGe hetero-junction bipolar transistors(SiGe HBTs) induced by bias stress are investigated in this review. If SiGe HBTs are stressed over a specific time interval, the device parameters deviate from their nominal values due to the internal changes in the devices. Reverse-bias stress on emitter-base(EB) junctions causes base current increase and current gain decrease because carriers accelerated by the electrical field generate recombination centers. When forward-bias current stress is conducted at an ambient temperature above $140^{\circ}C$ , hot carriers produced by Auger recombination or avalanche multiplication induce current gain fluctuation. Mixed-mode stressing, where high emitter current and high collector-base voltage are simultaneously applied to the device, provokes base current rise as EB reverse-bias stressing does.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.11
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• pp.1560-1565
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• 2013

This paper proposes the control method for compensating for unbalanced grid current and reducing a total harmonic distortion (THD) of the grid current at the three-phase grid-connected inverter systems under unbalancd and distorted grid voltage conditions. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for a minimum point of THD. Both the gain and angle of a compensation voltage at the minimum point of THD of the grid current are derived. The negative-sequence components in the three-phase unbalanced grid voltage are cancelled in order to achieve the balanced grid current. The simulation and experimental results show the validity of the proposed control methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.52-62
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analog current-mode active filters was proposed. Compared to the current-mode integrator which was proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter was designed with the proposed current-mode integrator. The designed circuits were fabricated using the ORBIT's 1.2.mu.m double-poly double-metal CMOS n-well process. The experimental resutls of the active filter designed and fabricated for this research have shown that it has the performance of 44.5MHz cutoff frequency, 3.3mW power dissipation and the third-order active filter area was 0.12mm$^{2}$.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.609-614
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• 1998

A new small signal modeling of an average current mode control is proposed. In order to analyze the characteristics of the control scheme, the discrete and continuous time small signal models are derived. The derivation are mainly come from the analysis of the sampling effect presented in the current control loop. By the mathematical interpretation of practical sampler representing the sampling effect of a current control loop, the small signal models of an average current mode control can be easily derived. The instability of the current control loop, which gives rise to the subharmonic oscillation, can be identified by the proposed models. To show the usefulness of the proposed models, the simulation and experiment are carried out. The results show that the predicted results by the proposed model are much better agreed with the measured ones than that of the conventional model, even though the high gain of the compensation network of a current control loop is employed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1726-1733
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• 1996

A 3V-50MHz analog CMOS continuous-time current-mode filter with a negative resistance load(NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. the inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5.mu.m CMOS n-well proess. Simulation result shows the cutoff frequency of 50MHz and power consumption of 2.4mW/pole with a 3V power supply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.67-70
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• 2000

In this paper, all SCR recombination currents including setback and graded layer's recombination currents are analytically introduced for the first time. Different emitter-base structures are tested to prove the validity of the model. In 1995, the analytical equations of electric field, electrostatic potential, and junction capacitance for abrupt and linearly graded heterojunctions with or without a setback layer was derived. But setback layer and linearly graded layer's recombination current was considered numerically. In this paper, recombination current model included setback layer and graded layer is proposed. New recombination current model also includes abrupt heterojunction's recombination current model. In this paper, new recombination current model analytically explains effects of setback layer and graded layer.