• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.562-567
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• 1996

A new lateral MOS controlled thyristor, named Shorted Anode LMCT(SA-LMCT), is proposed and analyzed by a two-dimensional device simulation. The device structure employs the implanted n+ layer which shorts the p+ anode together by a common metal electrode and provides a electron conduction path during turn-off period. The turn-off is achieved by not only diverting the hole current through the p+ cathode short but also providing the electron conduction path from the n-base into the n+ anode electrode. In addition, the modified shorted anode LMCT, which has an n+ short junction located inside the p+ anode junction, is also presented. It is shown that the modified SA-LMCT enjoys the advantage of no snap-back behavior in the forward characteristics with little sacrificing of the forward voltage drop. The simulation result shows that the turn-off times of SA-LMCT can be reduced by one-forth and the maximum controllable current density may be increased by 45 times at the expense of 0.34 V forward voltage drop as compared with conventional LMCT. (author). 11 refs., 6 figs., 1 tab.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.376-379
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• 2000

This paper presents an improved ZVS partial series resonant DC/DC converter (PSRC) with low conduction losses suitable for high power and high frequency applications. The proposed PSRC have advantages of zero-voltage-swiching (ZVS) of main switches for entire load ranges and low conduction losses of main switches by decreasing current stresses Also the reduction of the effective duty cycle is not occurred during the resonant period of the main circuit because the auxiliary circuit of the proposed converter is placed out of the main power path. An improved ZVS PSRC has a so much characteristics with respect to the reduction of current stress. The operation principles of the proposed converter are explained in detail and the various simulated and experimental results show the validity of the proposed converter.

• Journal of Power Electronics
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• v.14 no.4
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• pp.649-660
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• 2014

A novel non-isolated bidirectional soft-switching SEPIC/ZETA converter with reduced ripple currents is proposed and characterized in this study. Two auxiliary switches and an inductor are added to the original bidirectional SEPIC/ZETA components to form a new direct power delivery path between input and output. The proposed converter can be operated in the forward SEPIC and reverse ZETA modes with reduced ripple currents and increased voltage gains attributed to the optimized selection of duty ratios. All switches in the proposed converter can be operated at zero-current-switching turn-on and/or turn-off through soft current commutation. Therefore, the switching and conduction losses of the proposed converter are considerably reduced compared with those of conventional bidirectional SEPIC/ZETA converters. The operation principles and characteristics of the proposed converter are analyzed in detail and verified by the simulation and experimental results.

• Journal of Power Electronics
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• v.12 no.3
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.188.2-188.2
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• 2015

The presence of the conduction interface in epitaxial $LaAlO_3/SrTiO_3$ thin films has opened up challenging applications which can be expanded to next-generation nano-electronics. The metallic conduction path is associated with two adjacent insulating materials. Such device structure is applicable to frequency-dependent impedance spectroscopy. Impedance spectroscopy allows for simultaneous measurement of resistivity and dielectric constants, systematic identification of the underlying electrical origins, and the estimation of the electrical homogeneity in the corresponding electrical origins. Such unique capability is combined with the intentional control on the interface composition composed of $SrTiO_3$ and $CaTiO_3$, which can be denoted by $SrxCa1-_xTiO_3$. The underlying $Sr_xCa1-_xTiO_3$ interface was deposited using pulsed-laser deposition, followed by the epitaxial $LaAlO_3$ thin films. The platinum electrodes were constructed using metal shadow masks, in order to accommodate 2-point electrode configuration. Impedance spectroscopy was performed as the function of the relative ratio of Sr to Ca. The respective impedance spectra were analyzed in terms of the equivalent circuit models. Furthermore, the impedance spectra were monitored as a function of temperature. The ac-based characterization in the 2-dimensional conduction path supplements the dc-based electrical analysis. The artificial manipulation of the interface composition will be discussed towards the electrical application of 2-dimensional materials to the semiconductor devices in replacement for the current Si-based devices.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.4
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• pp.386-393
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• 2000

This paper presents an improved ZVS partial series resonant DC/DC converter (PSRC) with low conduction losses, suitable for high power and high frequency applications. The proposed PSRC have advantages of zero-voltage-switching (ZVS) of main switches for entire load ranges low conduction losses of main switches by decreasing current stresses. Also the reduction of the effective duty cycle is not occurred during the resonant period of the main circuit because the auxiliary circuit of the proposed converter is placed out of the main power path. The auxiliary circuit is composed with passive components, which are an inductor, two capacitors, two diodes, and a saturable inductor. An improved ZVS PSRC has so much characteristics with respect to the overall system efficiency and to the reduction of current stresses. The operation principles of the proposed converter are explained in detail and the various simulated and experimental results show the validity of the proposed converter.

• Journal of Power Electronics
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• v.12 no.5
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• pp.723-730
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• 2012

This paper presents a new ZVS single phase bridgeless (Power Factor Correction) PFC, using an active clamp to achieve zero-voltage-switching for all main switches and diodes. Since the presented PFC uses a bridgeless rectifier, most of the time, only two semiconductor components are in the main current path, instead of three in conventional single-switch configurations. This property significantly reduces the conduction losses,. Moreover, zero voltage switching removes switching loss of all main switches and diodes. Also, auxiliary switch turns on zero current condition. The presented converter needs just a simple non-isolated gate drive circuitry to drive all switches. The eight stages of each switching period and the design considerations and a control strategy are explained. Finally, the converter operation is verified by simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.759-762
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• 2014

비대칭 이중게이트(double gate; DG) MOSFET는 단채널 효과를 감소시킬 수 있는 새로운 구조의 트랜지스터이다. 본 연구에서는 비대칭 DGMOSFET의 전도중심에 따른 차단전류를 분석하고자 한다. 전도중심은 채널 내 캐리어의 이동이 발생하는 상단게이트에서의 평균거리로써 상하단 게이트 산화막 두께를 달리 제작할 수 있는 비대칭 DGMOSFET에서 산화막 두께에 따라 변화하는 요소이며 상단 게이트 전압에 따른 차단전류에 영향을 미치고 있다. 전도중심을 구하고 이를 이용하여 상단 게이트 전압에 따른 차단전류를 계산함으로써 전도중심이 차단전류에 미치는 영향을 산화막 두께 및 채널길이 등을 파라미터로 분석할 것이다. 차단전류를 구하기 위하여 포아송방정식으로부터 급수 형태의 해석학적 전위분포를 유도하였다. 결과적으로 전도중심의 위치에 따라 차단전류는 크게 변화하였으며 이에 따라 문턱전압 및 문턱전압이하 스윙이 변화하는 것을 알 수 있었다.

• Journal of Power Electronics
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• v.19 no.1
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• pp.296-306
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• 2019

The flyback topology is being widely used in power adapters. The coupling capacitance between primary and secondary windings of a flyback transformer is the main path for common-mode (CM) noise conduction. A Y-cap is usually used to effectively suppress EMI noise. However, this results in problems in space, cost, and the danger of safety leakage current. In this paper, the CM noise behaviors due to the electric field coupling of the transformer windings in a flyback adapter with synchronous rectification are analyzed. Then a scheme with balance winding is proposed to reduce the CM noise with a transformer winding design that eliminates the Y-cap. The planar transformer has advantages in terms of its low profile, good heat dissipation and good stray parameter consistency. Based on the proposed scheme, with the help of a full-wave simulation tool, the key parameter influences of the transformer PCB winding design on CM noise are further analyzed. Finally, a PCB transformer for an 18W adapter is designed and tested to verify the effectiveness of the balance winding scheme.