• 마이크로전자및패키징학회지
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• 제14권4호
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• pp.63-69
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• 2007

Cu 비아를 이용한 MEMS 센서의 스택 패키지용 interconnection 공정을 연구하였다. Ag 페이스트 막을 유리기판에 형성하고 관통 비아 홀이 형성된 Si 기판을 접착시켜 Ag 페이스트 막을 Cu 비아 형성용 전기도금 씨앗층으로 사용하였다. Ag 전기도금 씨앗층에 직류전류 모드로 $20mA/cm^2$와 $30mA/cm^2$의 전류밀도를 인가하여 Cu 비아 filling을 함으로써 직경 $200{\mu}m$, 깊이 $350{\mu}m$인 도금결함이 없는 Cu 비아를 형성하는 것이 가능하였다. Cu 비아가 형성된 Si 기판에 Ti/Cu/Ti metallization 및 배선라인 형성공정, Au 패드 도금공정, Sn 솔더범프 전기도금 및 리플로우 공정을 순차적으로 진행함으로써 Cu 비아를 이용한 MEMS 센서의 스택 패키지용 interconnection 공정을 이룰 수 있었다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 추계학술대회 초록집
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.12-12
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• 2008

Ruthenium is one of the noble metals having good thermal and chemical stability, low resistivity, and relatively high work function(4.71eV). Because of these good physical, chemical, and electrical properties, Ru thin films have been extensively studied for various applications in semiconductor devices such as gate electrode for FET, capacitor electrodes for dynamic random access memories(DRAMs) with high-k dielectrics such as $Ta_2O_5$ and (Ba,Sr)$TiO_3$, and capacitor electrode for ferroelectric random access memories(FRAMs) with Pb(Zr,Ti)$O_3$. Additionally, Ru thin films have been studied for copper(Cu) seed layers for Cu electrochemical plating(ECP) in metallization process because of its good adhesion to and immiscibility with Cu. We investigated Ru thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru thin films were grown by ALD(Lucida D100, NCD Co.) using RuDi as precursor and $O_2$ gas as a reactant at 200~$350^{\circ}C$.

• 한국전기전자재료학회논문지
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• 제34권5호
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• pp.333-336
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• 2021

Oxide YBCO bulk superconductors are manufactured using the melt process. Because seed crystal growth method utilizes a slow-spreading layer-by-layer reaction, a long-term heat treatment is required to manufacture a single-crystal specimen of several cm. In this study, the melt process method was applied to compensate for the shortcomings of the seed crystal growth method. The thickness of the upper and lower pellets of the YBCO bulk was molded to 40 mm, and YBCO superconductor was produced by heat treatment. The measurement results of capture magnetism was in line with the literature. This results in a relationship that the higher the growth of Y211 particle in the YBCO, the higher the superconducting properties. We analyzed the YBCO superconductor, focusing on the Y₂BaCuO₅ particle distribution.

• 대한금속재료학회지
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• 제48권1호
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• pp.90-100
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• 2010

Micro-conductive patterns were microfabricated on an insulating substrate ($SiO_2$) surface by a selective electroless nickel plating process in order to investigate the formation of seed layers. To fabricate micro-conductive patterns, a thin layer of metal (Cu.Cr) was deposited in the desired micropattern using laser-induced forward transfer (LIFT). and above this layer, a second layer was plated by selective electroless plating. The LIFT process. which was carried out in multi-scan mode, was used to fabricate micro-conductive patterns via electroless nickel plating. This method helps to improve the deposition process for forming seed patterns on the insulating substrate surface and the electrical conductivity of the resulting patterns. This study analyzes the effect of seed pattern formation by LIFT and key parameters in electroless nickel plating during micro-conductive pattern fabrication. The effects of the process variables on the cross-sectional shape and surface quality of the deposited patterns are examined using field emission scanning electron microscopy (FE-SEM) and an optical microscope.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.7-12
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• 2002

반도체 공정에서 구리(Cu) 배선의 미세구조와 신뢰성에 대해 연구하였는데, 특히 CVD Cu와 전기도금 Cu를 사용하여 신뢰성에 대한 texture와 결정 구조의 영향을 연구하였다 CVD Cu의 경우 여러 가지 시드층(seed layer)을 사용함으로서, 결정입자의 크기는 비슷하지만 texture가 전혀 다른 Cu 박막을 얻을 수 있었는데, 신뢰성 검사결과 (111) texture를 가진 Cu 배선의 수명이 (200) texture를 가진 Cu 배선의 수명보다 약 4배 가량 길게 나왔다. 전기도금 Cu 박막의 경우 항상 (111) texture를 갖고 있었으며 결정립의 크기도 CVD Cu의 것보다 더 컸다. Damascene 공법으로 회로 형성한 Cu 배선의 경우에도 전기도금 Cu의 결정립 크기가 CVD Cu의 것보다 더 크게 나타났으며, 신뢰성 검사결과 배선의 수명도 더 길게 나타났는데 그 차이는 0.4 $\mu\textrm{m}$ 이하의 미세선폭 영역에서 더욱 현저했다. 따라서 전기도금 Cu가 CVD Cu보다 신뢰성 측면에서 더 우수한 것으로 판명되었다.

• 한국전기전자재료학회논문지
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• 제23권7호
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• pp.575-579
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• 2010

The technologies of Ni/Cu plating contact is attributed to the reduced series resistance caused by a better contact conductivity of Ni with Si and the subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading was combined with the lower resistance of a metal silicide contact and an improved conductivity of the plated deposit. This improves the FF (fill factor) as the series resistance is reduced. This is very much requried in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A Selective emitter structure with highly dopeds regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing In this paper the formation of a selective emitter, and the nickel silicide seed layer at the front side metallization of silicon cells is considered. After generating the nickel seed layer the contacts were thickened by Cu LIP (light induced plating) and by the formation of a plated Ni/Cu two step metallization on front contacts. In fabricating a Ni/Cu plating metallization cell with a selective emitter structure it has been shown that the cell efficiency can be increased by at least 0.2%.

• 한국표면공학회지
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• 제56권4호
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• pp.219-226
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• 2023

Utilizing low-dimensional structures of oxide semiconductors is a promising approach to fabricate relevant gas sensors by means of potential enhancement in surface-to-volume ratios of their sensing materials. In this work, vertically aligned cupric oxide (CuO) nanorods are successfully synthesized on a transparent glass substrate via seed-mediated hydrothermal synthesis method with the use of a CuO nanoparticle seed layer, which is formed by thermally oxidizing a sputtered Cu metal film. Structural and optical characterization by x-ray diffraction (XRD), scanning electron microscopy (SEM), and Raman spectroscopy reveals the successful preparation of the CuO nanorods array of the single monoclinic tenorite crystalline phase. From gas sensing measurements for the nitrogen monoxide (NO) gas, the vertically aligned CuO nanorod array is observed to have a highly responsive sensitivity to NO gas at relatively low concentrations and operating temperatures, especially showing a high maximum sensitivity to NO at 200 ℃ and a low NO detection limit of 2 ppm in dry air. These results along with a facile fabrication process demonstrate that the CuO nanorods synthesized on a transparent glass substrate are very promising for low-cost and high-performance NO gas sensors.

• 마이크로전자및패키징학회지
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• 제17권3호
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• pp.79-84
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• 2010

3차원 Si 칩 패키징 공정을 위한 비아 홀(TSV: Through-Si-Via) 및 Au 시드층 형성, 전기 도금을 이용한 Cu 충전기술과 범핑 공정 단순화에 관하여 연구하였다. 비아 홀 형성을 위하여 $SF_6$ 와 $C_4F_8$ 플라즈마를 교대로 사용하는 DRIE(Deep Reactive Ion Etching) 법을 사용하여 Si 웨이퍼를 에칭하였다. 1.92 ks동안 에칭하여 직경 40 ${\mu}m$, 깊이 80 ${\mu}m$의 비아 홀을 형성하였다. 비아 홀의 옆면에는 열습식 산화법으로 $SiO_2$ 절연층을, 스퍼터링 방법으로 Ti 접합층과 Au 시드층을 형성하였다. 펄스 DC 전기도금법에 의해 비아 홀에 Cu를 충전하였으며, 1000 mA/$dm^2$ 의 정펄스 전류에서 5 s 동안, 190 mA/$dm^2$의 역펄스 조건에서 25 s 동안 인가하는 조건으로 총 57.6 ks 동안 전기도금하였다. Si 다이 상의 Cu plugs 위에 리소그라피 공정 없이 전기도금을 실시하여 Sn 범프를 형성할 수 있었으며, 심각한 결함이 없는 범프를 성공적으로 제조할 수 있었다.

• 한국세라믹학회지
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• 제35권8호
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• pp.827-835
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• 1998

Blanket Copper films were chemically vapor deposited on six kinds for substrates for scrutinizing the change of characteristics induced by the difference of substrates and seeding layers. Both TiN/Si and {{{{ { SiO}_{2 } }}/Si wafers were used as-recevied and with the Cu-seeding layers of 40${\AA}$ and 160${\AA}$ which were produced by sputtering The CVD processes were exectued at the deposition temperatures between 130$^{\circ}C$ and 260$^{\circ}C$ us-ing (hfc)Cu(VTMS) as a precursor. The deposition rate of 40$^{\circ}C$ Cu-seeded substrates was higher than that of other substrates and especially in seeded {{{{ { SiO}_{2 } }}/Si substrate because of the incubation period reducing in-duced by seeding layer at the same deposition time and temperature. The resistivity of 160${\AA}$ Cu seeded substrate was lower then that of 40 ${\AA}$ because the nucleation and growth behavior in Cu-island is different from the behavior in {{{{ { SiO}_{2 } }} substrate due to the dielectricity of {{{{ { SiO}_{2 } }}.