• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.57-58
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• 2006

Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

• 한국재료학회지
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• 제15권6호
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• pp.426-430
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• 2005

Chemical mechanical polishing (CMP) is an essential process in the production of integrated circuits containing copper interconnects. The effect of alanine in reactive slurries representative of those that might be used in copper CMP was studied with the aim of improving selectivity between copper(Cu) film and tantalum-nitride(TaN) film. We investigated the pH effect of nano-colloidal silica slurry containing alanine through the chemical mechanical polishing test for the 8(inch) blanket wafers as deposited Cu and TaN film, respectively. The copper and tantalum-nitride removal rate decreased with the increase of pH and reaches the neutral at pH 7, then, with the further increase of pH to alkaline, the removal rate rise to increase soddenly. It was found that alkaline slurry has a higher removal rate than acidic and neutral slurries for copper film, but the removal rate of tantalum-nitride does not change much. These tests indicated that alanine may improve the CMP process by controlling the selectivity between Cu and TaN film.

• 마이크로전자및패키징학회지
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• 제31권2호
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• pp.28-35
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• 2024

전자패키지 내부의 부식이 시스템 성능 및 신뢰성에 큰 영향을 미치고 있어, 시스템 건전성 관리를 위해 부식에 대한 비파괴적 진단 기법의 필요성이 커지고 있다. 본 연구에서는 복소 임피던스의 크기와 위상을 통합적으로 시각화하는 도구인 스미스 차트를 활용하여, 구리 인터커넥트의 부식을 비파괴적으로 평가하는 방법을 제시하고자 한다. 실험을 위해 구리 전송선을 모사한 시편을 제작하고, MIL-STD-810G 기준 온습도 사이클에 노출시켜 시편에 부식을 인가하였다. R 채널 기반 색변화로 시편의 부식도를 정량적으로 평가하고 레이블링 하였다. 부식의 성장에 따라 시편의 S-파라미터와 스미스 차트를 측정한 결과, 5 단계의 부식도에 따라 유의미한 패턴의 변화가 관찰되어, 스미스 차트가 부식도 평가에 효과적인 도구임을 확인하였다. 더 나아가 데이터 증강을 통해 다양한 부식도를 갖는 4,444개의 스미스 차트를 확보하여, 스미스 차트를 입력 받아 구리 인터커넥트의 부식 단계를 출력하는 인공지능 모델을 학습시켰다. 이미지 분류에 특화된 CNN 및 Transfomrer 모델을 적용한 결과, ConvNeXt 모델이 정확도 89.4%로 가장 높은 부식 진단 성능을 보였다. 스미스 차트를 이용하여 전자패키지 내부 부식을 진단할 경우, 전자신호를 이용하는 비파괴적 평가를 수행할 수 있다. 또한. 신호 크기와 위상 정보를 통합적으로 시각화 하여 직관적이며 노이즈에 강건한 진단이 가능할 것으로 기대한다.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.89-98
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• 2003

반도체 소자의 배선용 재료로서 사용가능한 합금원소 Mg를 첨가한 Cu(Mg) 박막의 기계 및 전기적 특성 변화를 조사하였다. Cu(2.7at.%Mg) 박막은 열처리를 할 경우 Cu 박막에 비하여 표면거칠기는 약 1/10 정도로 줄고 $SiO_2$와의 접착력도 2배 이상 향상된 결과를 나타내었다. 또한 $300^{\circ}C$이상의 온도에서 10분 이상 열처리를 할 경우 급격한 저항감소를 보여주었는데 이는 Mg 원소의 확산으로 인해 표면 및 계면에서 Mg 산화물이 형성되고 내부에는 순수 Cu와 같이 되었기 때문이다. 경도 및 열응력에 대한 저항력도 Cu박막에 비해 우수한 것으로 나타났으며 열응력으로 인해 Cu 박막에 나타나던 표면 void가 Cu(Mg) 박막에서는 전혀 관찰되지 않았다. EM Test 결과 lifetime은 2.5MA/$cm^2$, $297^[\circ}C$에서 순수 Cu 라인보다 5배 이상 길고 BTS Test 결과 Capacitance-Voltage 그래프의 플랫 밴드 전압(V$_{F}$ )의 shift현상이 Cu에서는 나타났지만 Cu(Mg) 박막에서는 발생하지 않는 우수한 신뢰성을 보여주었다. 누설전류 측정을 통한 $SiO_2$의 파괴시간은 Cu에 비하여 약 3배 이상 길어 합금원소에 의한 확산방지 효과가 있음을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.528-528
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• 2007

Cu CMP widely has been using for the formation of multilevel metal interconnects by the Cu damascene process. And lower dielectric constant materials are required for the below 45nm technology node. As the dielectric constant of dielectric materials are smaller, the strength of dielectric materials become weaker. Therefore these materials are easily damaged by high down pressure during conventional CMP. Also, technical problems such as surface scratches, delamination, dishing and erosion are also occurred. In order to overcome these problems in CMP, the ECMP (electro-chemical mechanical planarization) has been introduced. In this process, abrasive free electrolyte, soft pad and low down force were used. The electrolyte is one of important factor to solve these problems. Also, additives are required to improve the removal rate, uniformity, surface roughness, defects, and so on. In this study, KOH and $NaNO_3$ based electrolytes were used for Cu ECMP and the electrochemical behavior was evaluated by the potentiostat. Also, the Cu surface was observed by SEM as a function of applied voltage and chemical concentration.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.123-124
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• 2005

We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

• 마이크로전자및패키징학회지
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• 제28권2호
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• pp.59-64
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• 2021

차세대 반도체 기술은 이종소자 집적화(heterogeneous integration)를 이용한 시스템-인-패키징(system-inpackage, SIP) 기술로 발전하고 있고, 저온 Cu 본딩은 SIP 구조의 성능 향상과 미세 피치 배선을 위해서 매우 중요한 기술이라 하겠다. 본 연구에서는 porous한 Ag 나노막을 이용하여 Cu 표면의 산화 방지 효과와 저온 Cu 본딩의 가능성을 조사하였다. 100℃에서 200℃의 저온 영역에서 Ag가 Cu로 확산되는 것보다 Cu가 Ag로 확산되는 것이 빠르게 관찰되었고, 이는 저온에서 Ag를 이용한 Cu간의 고상 확산 본딩이 가능함을 나타내었다. 따라서 Ag 나노막을 이용한 Cu 본딩을 200℃에서 진행하였고, 본딩 계면의 전단 강도는 23.27 MPa로 측정되었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1999년도 추계학술발표강연 및 논문개요집
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• pp.84-84
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• 1999

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.117-123
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• 2014

써멀비아나 수직 배선으로 사용하기 위한 Cu 관통비아를 열린 비아 hole의 top-down filling 도금공정과 bottom-up filling 도금공정으로 형성 후 미세구조를 관찰하였다. 직류도금전류를 인가하면서 열린 비아 홀 내를 top-down filling 도금하거나 bottom-up filling 도금함으로써 내부기공이 없는 건전한 Cu 관통비아를 형성하는 것이 가능하였다. 열린 비아 홀의 top-down filling 공정에서는 Cu filling 도금 후 시편의 윗면과 밑면에서 과도금된 Cu 층을 제거하기 위한 chemical-mechanical polishing(CMP) 공정이 요구되는데 비해, 열린 비아 홀의 bottom-up filling 공정에서는 과도금된 Cu층을 제거하기 위한 CMP 공정이 시편 윗면에서만 요구되는 장점이 있었다.