• Title/Summary/Keyword: Cu Metallization

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Investigation of the Ni/Cu metal grid space for high-effiency, low cost crystlline silicon solar cells (고효율, 저가화 태양전지에 적합한 Ni/Cu 금속 전극 간격에 따른 특성 평가)

  • Kim, Min-Jeong;Lee, Ji-Hun;Cho, Kyeng-Yeon;Lee, Soo-Hong
    • 한국태양에너지학회:학술대회논문집
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    • 2009.04a
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    • pp.225-229
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    • 2009
  • The front metal contact is one of the most important element influences in efficiency in the silicon solar cell. First of all selective of the material and formation method is important in metal contacts. Commercial solar cells with screen-printed contacts formed by using Ag paste process is simple relatively and mass production is easy. But it suffer from a low fill factor and a high shading loss because of high contact resistance. Besides Ag paste too expensive. because of depends income. This paper applied for Ni/Cu metallization replace for paste of screen printing front metal contact. Low cost Ni and Cu metal contacts have been formed by using electroless plating and electroplating techniques to replace the screen-printed Ag contacts. Ni has been proposed as a suitable silicide for the salicidation process and is expected to replace conventional silicides. Copper is a promising material for the electrical contacts in solar cells in terms of conductivity and cost. In experiments Ni/Cu metal contact applied same grid formation of screen-printed solar cell. And it has variation of different grid spacing. It was verified that the wide spacing of grid finger could increase the series resistance also the narrow spacing of grid finger also implies a grid with a higher density of grid fingers. Through different grid spacing found alteration of efficiency.

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Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging (첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향)

  • Eun-Chae Noh;Hyo-Won Lee;Jeong-Won Yoon
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.1-10
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    • 2023
  • Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.

Characteristics and Physical Property of Tungsten(W) Related Diffusion Barrier Added Impurities (불순물을 주입한 텅스텐(W) 박막의 확산방지 특성과 박막의 물성 특성연구)

  • Kim, Soo-In;Lee, Chang-Woo
    • Journal of the Korean Vacuum Society
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    • v.17 no.6
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    • pp.518-522
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    • 2008
  • The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

A Study on the Characteristics of Sn-Cu Solder Bump for Flip Chip by Electroplating (전해도금에 의한 플립칩용 Sn-Cu 솔더범프의 특성에 관한 연구)

  • Jung, Seok-Won;Hwang, Hyun;Jung, Jae-Pil;Kang, Chun-Sik
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.11a
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    • pp.49-53
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    • 2002
  • The Sn-Cu eutectic solder bump formation ($140{\mu}{\textrm}{m}$ diameter, $250{\mu}{\textrm}{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Cu deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased with increasing time. The plating rate increased generally according to current density. After the characteristics of Sn-Cu plating were investigated, Sn-Cu solder bumps were fabricated on optimal condition of 5A/dm$^2$, 2hrs. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallization). The shear strength of Sn-Cu bump after reflow was higher than that of before reflow.

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A bilayer diffusion barrier of atomic layer deposited (ALD)-Ru/ALD-TaCN for direct plating of Cu

  • Kim, Soo-Hyun;Yim, Sung-Soo;Lee, Do-Joong;Kim, Ki-Su;Kim, Hyun-Mi;Kim, Ki-Bum;Sohn, Hyun-Chul
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.239-240
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    • 2008
  • As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

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Characteristics of Molybdenum Nitride Diffusion Barrier for Copper Metallization (Cu 금속배선을 위한 Molybdenum Nitride 확산 방지막 특성)

  • Lee, Jeong-Yeop;Park, Jong-Wan
    • Korean Journal of Materials Research
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    • v.6 no.6
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    • pp.626-631
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    • 1996
  • Reactive dc magnetron sputtering 법을 이용하여 증착한 molybdenum mitride 박막의 Cu 확산 방지막 특성을 조사하였다. Cu 확산 방지막으로서 molybdenum nitride 박막의 열적안정성을 관찰하기 위하여 molybdenum nitride 박막 위에 Cu를 evaporation 법으로 증착하고 진공 열처리하였다. Cu/r-Mo2N/si 구조는 $600^{\circ}C$, 30분간 열처리 시까지 안정하였다. 확산 방지막의 파괴는 $650^{\circ}C$, 30분간 열처리 시부터 격자 확산(lattice diffusion)이나 입계(grain boundary)과 결함(defect)을 통한 확산에 의해 나타나기 시작하였고, 이 때 molybdenum silicide과 copper silicide의 형성에 기인된 것으로 생각되었다. 열처리 이후 Cu/r-Mo2N/Si 사이의 상호반응이 증가하였다. 이는 Rutherford backscattering spectrometry, Auger electron spectroscopy 그리고 Nomarski microscopy 등의 분석을 통해 조사되었다.

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A Study on Cu(B)/Ti/SiO2/Si Structure for Application to Advanced Manufacturing Process (차세대 공정에 적용 가능한 Cu(B)/Ti/SiO2/Si 구조 연구)

  • Lee Seob;Lee Jaegab
    • Korean Journal of Materials Research
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    • v.14 no.4
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    • pp.246-250
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    • 2004
  • We have investigated the effects of boron added to Cu film on the Cu-Ti reaction and microstructural evolution of Cu(B) alloy film during annealing of Cu(B)/Ti/$SiO_2$/Si structure. The result were compared with those of Cu(B)/$SiO_2$ structure to identify the effects of Ti glue layers on the Boron behavior and the result grain growth of Cu(B) alloy. The vacuum annealing of Cu(B)/Ti/$SiO_2$ multilayer structure allowed the diffusion of B to the Ti surface and forming $TiB_2$ compounds at the interface. The formed $TiB_2$ can act as a excellent diffusion barrier against Cu-Ti interdiffusion up to $800^{\circ}C$. Also, the resistivity was decreased to $2.3\mu$$\Omega$-cm after annealing at $800^{\circ}C$. In addition, the presence of Ti underlayer promoted the growth Cu(l11)-oriented grains and allowed for normal growth of Cu(B) film. This is in contrast with abnormal growth of randomly oriented Cu grains occurring in Cu(B)/$SiO_2$ upon annealing. The Cu(B)/Ti/$SiO_2$ structure can be implemented as an advanced metallization because it exhibits the low resistivity, high thermal stability and excellent diffusion barrier property.

Formation of Sn-Cu Solder Bump by Electroplating for Flip Chip (플립칩용 Sn-Cu 전해도금 솔더 범프의 형성 연구)

  • 정석원;강경인;정재필;주운홍
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.4
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    • pp.39-46
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    • 2003
  • Sn-Cu eutectic solder bump was fabricated by electroplating for flip chip and its characteristics were studied. A Si-wafer was used as a substrate and the UBM(Under Bump Metallization) of Al(400 nm)/Cu(300 nm)/Ni(400 nm)/Au(20 nm) was coated sequentially from the substrate to the top by an electron beam evaporator. The experimental results showed that the plating ratio of the Sn-Cu increased from 0.25 to 2.7 $\mu\textrm{m}$/min with the current density of 1 to 8 A/d$\m^2$. In this range of current density the plated Sn-Cu maintains its composition nearly constant level as Sn-0.9∼1.4 wt%/Cu. The solder bump of typical mushroom shape with its stem diameter of 120 $\mu\textrm{m}$ was formed through plating at 5 A/d$\m^2$ for 2 hrs. The mushroom bump changed its shape to the spherical type of 140 $\mu\textrm{m}$ diameter by air reflow at $260^{\circ}C$. The homogeneity of chemical composition for the solder bump was examined, and Sn content in the mushroom bump appears to be uneven. However, the Sn distributed more uniformly through an air reflow.

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