• Journal of the Korea Institute of Building Construction
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• v.13 no.6
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• pp.565-578
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• 2013

Batch production is common in repetitive construction projects, and it is not unusual for different batch sizes to be used by contractors in one project. While several scheduling methods, such as the Linear Scheduling Method (LSM) and the Repetitive Scheduling Method (RSM) have been proposed and used, no mathematical method for repetitive construction projects has been developed, and it is difficult to consider different batch sizes with the existing methods. An original mathematical algorithm for scheduling repetitive projects with different batch sizes is proposed in this study. This algorithm is illustrated with assumptions of resource continuity and single path in a project and introduces new terms, control batch and critical batch. The algorithm logics and mathematical equations are validated by comparison with the outcomes from a graphical scheduling approach through a simple and practical hypothetic project. As a result, it is expected that the proposed algorithm can be easily adapted and extended to computer software for scheduling, and can be a starting point for research on batch size management in repetitive construction projects.

• Journal of Korean Association for Spatial Structures
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• v.16 no.1
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• pp.53-64
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• 2016

Solar power is being spotlighted recently as a new energy source due to environmental problems and applications of solar power to curved structures are increasing. Solar panels installed on curved surfaces have different efficiencies depending on its position and the efficient positioning of solar panels plays a critical role in the design of solar power generation systems. In this study, the changing characteristics of solar irradiance were analyzed for hemispherical dome with a large curvature and the positioning of solar panels that can efficiently utilize solar energy was investigated. With an icosahedron-based hemispherical dome consisting of triangular elements as target model, a program for calculating solar irradiance using a normal vector of the solar module on each face was developed. Furthermore, the change of solar irradiance according to the sun's path was analyzed by time and season, and its effects on shades were also examined. From the analysis results, the effective positioning could be determined on the basis of the efficiency of the solar panels installed on the dome surfaces on solar irradiance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.172-179
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• 2015

Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.7
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• pp.364-369
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• 2002

In this paper, 3-D magnetostatic finite element simulation of a rotux type Low-Tc superconducing (LTS) superconducting power supply, finite element method, cryogenic system, superconducting foil by generated magnetic flux from the rotating pole. The magnetic flux density on the superconducting foil caused by two exciters is therefore sufficiently greater than its critical magnetic flux density and it is an essential point in LTS power supply design. To establish the sufficient flux path of this machine, ferromagnetic materials is used in this power supply. When ferromagnetic materials is used at extremely low temperature, its characteristic of magnetization differs to that at room temperature. For this reason, special consideration is needed in the magnetic analysis of cryogenic systems. When the excitation current is 10A, the normal spot appears on superconducting foil. The results of this analysis are calculated and compared with the experimental results. The linkage flux due to the excitation current of 10, 20, 30, 40 and 50A are respectively $1.30{\times}10-4$, $2.67{\times}10-4$, $5.08{\times}10-4$ and $6.15{\times}10-4Wb$.

• KDI Journal of Economic Policy
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• v.36 no.1
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• pp.107-126
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• 2014

The core of the neoclassical growth theory is the capital investment. Solow proposed that the diminishing return is key to such growth process in establishing the stability of the equilibrium growth path. This key postulation has critical implications on the sustainable and effective development policies, emphasizing the importance of productivity growth not only for the steady-state growth but also for the transitional growth from capital accumulation. This paper suggests a novel way to test the diminishing return, the backbone assumption of Solow model, and confirms its strong presence using the Penn World Tables version 8.0 data, hence validates Solow's implications on effective development policies.

• The Journal of Information Technology
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• v.2 no.2
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• pp.145-161
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• 1999

This paper proposes a high speed back propagation neural networks which uses the residue number system. making the high speed operation possible without carry propagation Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed, The Designed circuits are descripted by VHDL and synthesized by Compass tools. Result of simulations shows that critical path delay time is about 19nsec and the size can be reduced to 40% compared to the neural networks implemented by the real number operation unit. The proposed design circuits can be implemented in parallel distributed processing system with desired real time processing.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.8
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• pp.3350-3365
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• 2020

A considerable literature has recently grown up on the theme of ship wireless communications. However, much of the research up to now has been descriptive in the offshore area. There has been little quantitative analysis of wireless communication in inland waterways, which has received considerable attention lately. Until now, only the effects on inland river environment are examined. What is less clear is the nature of channel change caused by the antenna movement. Here we explore the moving ship-to-fixed-ship fading characteristics at 5.9 GHz for an inland waterway in the city center of China. The ship motion trajectory is designed in order to determine the effect of changes in the antenna position. We evaluate the channel fading characteristics of inland waterway, which are highly correlated with the distance between transmitter and receiver. We demonstrate that the line-of-sight component, as well as the components from multipath with obstruction reflections, contributes largely to the mean power gap. Our findings reveal critical ship-to-ship characteristics in inland waterway, which definitely contribute to the field of ship wireless communications.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.37-44
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• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.