Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Architecture Design of Line based Lifting-DWT for JPEG2000 Image Compression

JPEG2000영상압축을 위한 라인 기반의 리프팅 DWT 구조 설계

  • Published : 2004.11.01
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Abstract

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

본 논문은 JPEG2000의 손실 압축 또는 무손실 압축에 사용되어지는 9-7/5-3 리프팅 DWT필터에 대한 효율적인 VLSI 구조를 제안한다. 제안된 구조는 리프팅 DWT 연산을 위해 내부 라인 메모리만을 사용하며, 내부 처리 유닛은 1개의 곱셈기와 1개의 덧셈기의 임계경로를 갖는다. 특히 본 논문에서는 처리유닛의 수를 감소하기 위해 1레벨의 열방향을 담당하는 필터로 하여금 2레벨 이상의 행방향과 열방향 연산 모두를 처리하도록 하였다. 결과적으로 제안된 구조는 기존의 구조에 비해 작은 하드웨어 크기를 갖는다. 제안된 리프팅 DWT구조는 RTL 수준에서 VHDL로 모델링되었으며, 기능 검증 후 Altera APEX 20K FPGA로 구현되었다.

Keywords

References

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