• Title/Summary/Keyword: Coverage Testing

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Development of Optimized State Assignment Technique for Testing and Low Power (테스팅 및 저전력을 고려한 최적화된 상태할당 기술 개발)

  • Cho Sangwook;Yi Hyunbean;Park Sungju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.1
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    • pp.81-90
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    • 2004
  • The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.

LOS/LOC Scan Test Techniques for Detection of Delay Faults (지연고장 검출을 위한 LOS/LOC 스캔 테스트 기술)

  • Hur, Yongmin;Choe, Youngcheol
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.4
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    • pp.219-225
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    • 2014
  • The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

A Case Study of Community without Propinquity : focused on Topgol Comic Book Space in Goesan, Chungbuk (근접성 없는 공동체의 사례 연구 - 충북 괴산 탑골 만화방을 대상으로 -)

  • Lee, Jung-Min;Lee, Man-Hyung;Hong, Sung-Ho
    • Journal of the Korean association of regional geographers
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    • v.22 no.3
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    • pp.655-665
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    • 2016
  • The meanings and roles of community have been changed. Traditional community theories hinged on the neighborhood have been threatened by the alternative concept of 'communities without propinquity'. Embracing unprecedented development of transportation, information and communication technologies, Propinquity of community has not been a precondition. This paper reviews the development of community theories with a frame of 'communities without propinquity'. Furthermore, applying social network analysis(SNA) approaches, it explores the communality of Topgol Comic Book Space, located in Goesan, Chungbuk and examines spatial characters. Visitors' networks of Topgol Comic Book Space builda up national coverage and expands. It functions as a field of testing various activities without explicit 'fixed purpose'. The case exemplifies a community, continuously enlarging the spatial and social boundaries, performing a series of activities, and connecting both the outside and the local.

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Determinants of Potentially Unnecessary Cervical Cancer Screenings in American Women

  • Seo, Munseok;Langabeer, James
    • Journal of Preventive Medicine and Public Health
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    • v.51 no.4
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    • pp.181-187
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    • 2018
  • Objectives: To identify factors responsible for potentially clinically unnecessary cervical cancer screenings in women with prior hysterectomy. Methods: A retrospective cross-sectional study was conducted using the Centers for Disease Control and Prevention's Behavioral Risk Factor Surveillance System (BRFSS). This study targeted adult women and examined whether they received a both a Papanicolaou (Pap) test and undergone a hysterectomy in the last three years. We conducted multivariate analyses, including weighted proportions and odds ratios (ORs), based on the modified BRFSS weighting method (raking). The inclusion criteria were adult women (>18 years old) who reported having received a Pap test within the last 3 years. Results: Of all women (n=252 391), 72 366 had received a Pap test, and 32 935 of those women (45%, or 12.5 million, weighted) had a prior hysterectomy. We found that age, race/ethnicity, marital status, family income, health status, time since last routine checkup, and health insurance coverage were all significant predictors. Black, non-Hispanic women were 2.23 times more likely to receive Pap testing after a hysterectomy than white women (OR, 2.23; 95% confidence interval [CI], 1.99 to 2.50). Similarly, the odds for Hispanic women were 2.34 times higher (OR, 2.34; 95% CI, 1.97 to 2.80). The odds were also higher for those who were married (OR, 1.17; 95% CI, 1.08 to 1.27), healthier (OR, 1.24; 95% CI, 1.14 to 1.35), and had health insurance (OR, 1.54; 95% CI, 1.28 to 1.84), after controlling for confounders. Conclusions: We conclude that women may potentially receive Pap tests even if they are not at risk for cervical cancer, and may not be adequately informed about the need for screenings. We recommend strategies to disseminate recommendations and information to patients, their families, and care providers.

Specification-based Analog Circuits Test using High Performance Current Sensors (고성능 전류감지기를 이용한 Specification 기반의 아날로그 회로 테스트)

  • Lee, Jae-Min
    • Journal of Korea Multimedia Society
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    • v.10 no.10
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    • pp.1260-1270
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    • 2007
  • Testing and diagnosis of analog circuits(or mixed-signal circuits) continue to be a hard task for test engineers and efficient test methodologies to solve these problems are needed. This paper proposes a novel analog circuits test technique using time slot specification (TSS) based built-in current sensors (BICS). A technique for location of a fault site and separation of fault type based on TSS is also presented. The proposed built-in current sensors and TSS technique has high testability, fault coverage and a capability to diagnose catastrophic faults and parametric faults in analog circuits. In order to reduce time complexity of test point insertion procedure, external output and power nodes are used for test points and the current sensors are implemented in the automatic test equipment(ATE). The digital output of BICS can be easily combined with built-in digital test modules for analog IC test.

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A Length-based File Fuzzing Test Suite Reduction Algorithm for Evaluation of Software Vulnerability (소프트웨어 취약성 평가를 위한 길이기반 파일 퍼징 테스트 슈트 축약 알고리즘)

  • Lee, Jaeseo;Kim, Jong-Myong;Kim, SuYong;Yun, Young-Tae;Kim, Yong-Min;Noh, Bong-Nam
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.23 no.2
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    • pp.231-242
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    • 2013
  • Recently, automated software testing methods such as fuzzing have been researched to find software vulnerabilities. The purpose of fuzzing is to disclose software vulnerabilities by providing a software with malformed data. In order to increase the probability of vulnerability discovery by fuzzing, we must solve the test suite reduction problem because the probability depends on the test case quality. In this paper, we propose a new method to solve the test suite reduction problem which is suitable for the long test case such as file. First, we suggested the length of test case as a measure in addition to old measures such as coverage and redundancy. Next we designed a test suite reduction algorithm using the new measure. In the experimental results, the proposed algorithm showed better performance in the size and length reduction ratio of the test suite than previous studies. Finally, results from an empirical study suggested the viability of our proposed measure and algorithm for file fuzzing.

Ka-Band Antenna Design Using the Reflector Shaping for the Communications & Broadcasting Satellite (반사판 표면성형기법을 적용한 통신방송위성 Ka대역 안테나의 설계)

  • Han, Jae-Hung;Yun, So-Hyeun;Park, Jong-Heung;Lee, Seong-Pal
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.32 no.4
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    • pp.88-94
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    • 2004
  • The electrical design of the Ka-band antenna for the domestic Communications and Broadcasting Satellite (CBS) is described. The antenna has the offset Gregorian structure and is installed on the Earth-facing panel of the satellite. The electrical performance specifications for the antenna were determined from the required EIRP and G/T through the payload level performance analysis. This paper utilized the reflector shaping technology for the trade-off among the major performance parameters, resulting in compliance of all the parameters. The designed antenna shows 37.95 dBi EOC (End of Coverage) gain and 28.7 dB sidelobe isolation for transmit band, and 37.49 dBi EOC gain and 31.1 dB sidelobe isolation for receive band, The electrical performances of the antenna have been verified via the electrical testing of a manufactured EQM (Engineering Qualification Model) antenna.

IEEE std. 1500 based an Efficient Programmable Memory BIST (IEEE 1500 표준 기반의 효율적인 프로그램 가능한 메모리 BIST)

  • Park, Youngkyu;Choi, Inhyuk;Kang, Sungho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.114-121
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    • 2013
  • As the weight of embedded memory within Systems-On-Chips(SoC) rapidly increases to 80-90% of the number of total transistors, the importance of testing embedded memory in SoC increases. This paper proposes IEEE std. 1500 wrapper based Programmable Memory Built-In Self-Test(PMBIST) architecture which can support various kinds of test algorithm. The proposed PMBIST guarantees high flexibility, programmability and fault coverage using not only March algorithms but also non-March algorithms such as Walking and Galloping. The PMBIST has an optimal hardware overhead by an optimum program instruction set and a smaller program memory. Furthermore, the proposed fault information processing scheme guarantees improvement of the memory yield by effectively supporting three types of the diagnostic methods for repair and diagnosis.

A Study on the Management Efficiency Effect Factor of Korean Ocean Carriers

  • Hong, Sog-Min;Ahn, Ki-Myung
    • Journal of Navigation and Port Research
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    • v.44 no.2
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    • pp.119-127
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    • 2020
  • In this study, the current state of management efficiency of ocean carriers in Korea and the factors affecting them were analyzed. The purpose of this research is to enhance global competitiveness of ocean carriers by presenting suggestions that can improve management efficiency based on the analysis results. The measurement of management efficiency was made using the DEA model. The results of testing the adequacy of the input and output variables used are as follows. Appropriate inputs are total assets, cost of goods sold, charter expenses, sales and general management expenses, and interest expenses. Appropriate variables are sales, operating income, and operating cash flow. According to the analysis results of the DEA model by these variables, inefficient carriers (78%) are nearly four times more than efficient carriers(22%). However, container carriers have the most improved management efficiency compared to 2016 and 2017. According to the panel regression analysis, the charter rate has the greatest negative impact on efficiency (CRS), and the debt rate has a significant negative impact. Thus, it appears that reducing the charter size and the debt-to-sale rate facilitate improvement of the management efficiency of ocean carriers. Additionally, the pre-sales tax return rate, value added rate, total asset turnover rate, and the scale variable and interest coverage rate have a positive (+) effect. Thus ocean carriers should restore their global competitiveness by improving management efficiency by securing stable cargoes increasing sales profitability from the cost management perspective, increasing productivity, and enhancing the efficiency of their total assets through efficient fleet management.

A New Low Power Scan BIST Architecture Based on Scan Input Transformation Scheme (스캔입력 변형기법을 통한 새로운 저전력 스캔 BIST 구조)

  • Son, Hyeon-Uk;Kim, You-Bean;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.43-48
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    • 2008
  • Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.