• The Bulletin of The Korean Astronomical Society
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• v.33 no.2
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• pp.58.2-58.2
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• 2008

• Proceedings of the Korean Magnestics Society Conference
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• 1998.10a
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• pp.78-79
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• 1998

• The Journal of Korean Academy of Prosthodontics
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• v.30 no.4
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• pp.493-497
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• 1992

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.262-265
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• 2007

Metallic sandwich plates constructed of two face sheets and low relative density cores have lightweight characteristics and various static and dynamic load bearing functions. To predict the formability and performance of these structured materials, a computationally efficient FE-analysis method incorporating virtual equivalent projected model has been newly introduced for analysis of metallic sandwich plates. Two dimensional models using the projected shapes of 3D structures have the same equivalent elastic-plastic properties with original geometries including anisotropic stiffness, yield strength and linear hardening function. The projected shapes and virtual properties of the virtual equivalent projected model have been estimated analytically with the same equivalent properties and face buckling strength of 3D pyramidal truss core.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

• Journal of IKEEE
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• v.16 no.3
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• pp.197-202
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• 2012

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Transactions of Materials Processing
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• v.16 no.7
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• pp.549-554
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• 2007

The objective of this paper is to investigate into the fabrication technology of cores for the injection mould with three-dimensional conformal cooling channels to reduce the cooling time. The location of the conformal cooling channels has been determined through the injection molding analysis. The mould has been manufactured from a hybrid rapid tooling technology, which is combined a direct metal rapid tooling with a machining process. Several injection molding experiments have been performed to examine the productivity and the validity of the designed mould. From the results of the experiments, it has been shown that the proposed mould can mold a final product within a cooling time of 3 seconds and a cycle time of 21 seconds, respectively.

• Proceedings of the Korean Nuclear Society Conference
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• 1997.05a
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• pp.495-501
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• 1997

A preliminary and parametric sensitivity study on recriticality risk of fast reactor cores after a hypothetical total core meltdown accident was performed. Only neutronic aspects of the accident were considered, independent of the accident scenario, and efforts were made to estimate the quantity of molten fuel which must be ejected out of the core to assure a sub-critical state after the accident. Two types of parameters were examined : characteristic parameters of molten core such as geometry, molten pool type (homogenized or stratified), fuel temperature, environment, and relative parameters to normal core such as core size(small or large), and fuel type (oxide, nitride, metal). The first type of parameters was found to intervene more directly in the recriticality risk than the second type of parameters.