• The Journal of Korean Institute of Communications and Information Sciences
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• 제32권9A호
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• pp.931-939
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• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• 제13권4호
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• pp.306-311
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• 2020

This paper deals with how to improve the performance of Python language with various libraries when developing a model using big data. The Python language uses the Pandas library for processing spreadsheet-format data such as Excel. In processing data, Python operates on an in-memory basis. There is no performance issue when processing small scale of data. However, performance issues occur when processing large scale of data. Therefore, this paper introduces a method for distributed processing of execution tasks in a single cluster and multiple clusters by using a Dask library that can be used with Pandas when processing data. The experiment compares the speed of processing a simple exponential model using only Pandas on the same specification hardware and the speed of processing using a dask together. This paper presents a method to develop a model by distributing a large scale of data by CPU cores in terms of performance while maintaining that python's advantage of using various libraries is easy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.367-370
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.11i wireless LAN security. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining)mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 25% compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 15,450 gates, and the estimated throughput is about 128 Mbps at 50-MHz clock frequency). The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Proceedings of the KIEE Conference
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• 대한전기학회 2002년도 학술대회 논문집 전문대학교육위원
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• pp.187-190
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• 2002

In contrast to conventional electromagnetic motor, USM(Ultrasonic Motor), as piezoelectric ceramic applying ultrasonic mechanical vibration and as frictional-movement type motor, get rotational torque by elastic friction between stator and rotator, The USM, which is small motor without iron cores and coil as a simple structure, has little load weight, has character of high torque at low speed, and can apply a direct drive type without deceleration gear as low speed type. A response of USM from control input is satisfactory, and also generates much torque in low speed driving, and holding torque is much without supplying power. In this study, I designed and made Ultrasonic motor-digital multi controller(USM- DMC) using FPGA chip, A54SX72A made in Actel Corporation. By the minute, USM-DMC can control frequency, duty ratio, and phase difference of USM by llbit digital input from Pc. Therefore, when we use this controller, we can apply to typical parameter, frequency, phase difference, and voltage parameter, to control as well as we can do mixing control like phase-frequency, phase-voltage, frequency-voltage, frequency-phase-voltage, What is more, the strongest point is that it can trace frequency based on optimized frequency because we can input optimized resonant frequency while in motoring.

• The Transactions of the Korean Institute of Power Electronics
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• 제10권6호
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• pp.592-597
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• 2005

The push pull forward converter is suitable in a low output voltage, a high output current applications with wide input voltage ranges. All magnetic components including output inductor, transformer and input filter can be integrated into single EI/EE core. The integrated push pull forward converter is considered through the comparison of efficiency according to the circuit parameters. The Nicera company's 5M FEE18/8/10C and NC-2H FEI32/8/20 cores are used for the transformer. The integrated push pull forward converter ratings are of $36\~72V$ input and 3.3V/30A output. In case that NC-2H FEI32/8/20 core used in the converter, the efficiency is measured up to $83.5\%$ at the switching frequency 200 kHz and the 11A load. The efficiencies of $76.4\%$ at a full load and $82.95\%$ at a half load are measured.

• The Transactions of the Korean Institute of Power Electronics
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• 제16권3호
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• pp.242-249
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• 2011

The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.

• Journal of Korean Society of Coastal and Ocean Engineers
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• 제24권5호
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• pp.352-365
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• 2012

A primary study on the rapid modeling of storm surge, which is one of typical coastal disasters, for immediate forecasting in conjunction with typhoon advisories is done and tested for the typhoons Bolaven, Tembin and Sanba which attacked to Korean Peninsula on August and September in this year 2012. Semi automatic rapid computations according to JTWC typhoon advisories were performed and uploaded to the web by models SLOSH in PC and ADCIRC in parallel clusters with 64 cores having 57k nodes encompassing the North-Western Pacific region. It only takes 1 and 2 hours from taking advisory to web uploading, respectively. By comparison with observed water surface elevations for the major tidal stations after Bolaven attack it shows within RMS error of 0.17~0.19 m for surge heights and only deviates 1 hour of peak surge time in ADCIRC model. Thus it is concluded that this approach provides a frame of near real-time immediate forecasting of storm surges with satisfactions.

• Journal of Satellite, Information and Communications
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• 제9권4호
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• 제8권2호
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• pp.135-142
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• 2010

To obtain the input data for the design and long-term performance assessment of a high-level waste repository, the thermal conductivities of several granite rocks which were taken from the rock cores from the declined borehole were measured. The thermal conductivities of granite were measured under the different conditions of water content to investigate the effects of the water content on the thermal conductivity. A simple empirical correlation was proposed to predict the thermal conductivity of granite as a function of effective porosity and water content which can be measured with relative ease while neglecting the possible effects of mineralogy, structure and anisotropy. The correlation could predict the thermal conductivity of granite with the effective porosity below 2.7% from the KURT site with an estimated error below 10%.

• Journal of KIISE
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• 제43권1호
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• pp.61-70
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• 2016

In recent years, there has been a need for techniques for large-scale ontology inference in order to infer new knowledge from existing knowledge at a high speed, and for a diversity of semantic services. With the recent advances in distributed computing, developments of ontology inference engines have mostly been studied based on Hadoop or Spark frameworks on large clusters. Parallel programming techniques using GPGPU, which utilizes many cores when compared with CPU, is also used for ontology inference. In this paper, by combining the advantages of both techniques, we propose a new method for reasoning large RDFS ontology data using a Spark in-memory framework and inferencing distributed data at a high speed using GPGPU. Using GPGPU, ontology reasoning over high-capacity data can be performed as a low cost with higher efficiency over conventional inference methods. In addition, we show that GPGPU can reduce the data workload on each node through the Spark cluster. In order to evaluate our approach, we used LUBM ranging from 10 to 120. Our experimental results showed that our proposed reasoning engine performs 7 times faster than a conventional approach which uses a Spark in-memory inference engine.