• Proceedings of the KIPE Conference
• /
• 2013.07a
• /
• pp.386-387
• /
• 2013

This paper provides a comparison of high power semiconductor devices in 5MW-class Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) wind turbines. High power semiconductor devices of IGBT module type, IGBT press-pack type, and IGCT of both 4.5kV and 6.5kV are considered in this paper. Benchmarking is performed based on neutral-point clamed 3-level back-to-back type voltage source converter supplied from grid voltage of 4160V. The feasible number of semiconductor devices in parallel is designed through the loss analysis considering both conduction and switching losses under the given operating conditions of 5MW-class PMSG wind turbines, particularly for the application in offshore wind farms. The loss analysis is confirmed through PLECS simulations. The comparison result shows that IGBT press-pack type semiconductor device has the highest efficiency and IGCT has the lowest cost factor considering the necessary auxiliary components.

• Journal of Power Electronics
• /
• v.10 no.6
• /
• pp.686-693
• /
• 2010

In this paper, a fault diagnosis method based on fuzzy logic for the three-parallel power converter in a wind turbine system is presented. The method can not only detect both open and short faults but can also identify faulty switching devices without additional voltage sensors or an analysis modeling of the system. The location of a faulty switch can be indicated by six-patterns of a stator current vector and the fault switching device detection is achieved by analyzing the current vector. A fault tolerant algorithm is also presented to maintain proper performance under faulty conditions. The reliability of the proposed fault detection technique has been proven by simulations and experiments with a 10kW simulator.

• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.367-368
• /
• 2014

This paper investigates characteristics of high power semiconductor device losses in 5MW-class Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) wind turbines. High power semiconductor device of press-pack type IGCT of 6.5kV is considered in this paper. Analysis is performed based on neutral point clamped (NPC) 3-level back-to-back type voltage source converter (VSC) supplied from grid voltage of 4160V. This paper describes total loss distribution at worst case under inverter and rectifier operating mode for the power semiconductor switches. The loss analysis is confirmed through PLECS simulations. In addition, the loss factors due to di/dt snubber and ac input filter are presented. The investigation result shows that IGCT type semiconductor devices generate the total efficiency of 97.74% under the rated condition.

• Proceedings of the KIEE Conference
• /
• 2005.10c
• /
• pp.253-256
• /
• 2005

In this paper, doubly-fed induction-type wind power generation system simulation model for grid connection is developed. The simulation model is based on PSCAD/EMTDC and consists of rotor-blade, generator, power converter and controller. Simulation results are shown for the variable wind speed conditions. The simulation model can be utilized for study of actual interaction between wind turbine and grid for reliable operation and protection of power system.

• Journal of Power Electronics
• /
• v.19 no.2
• /
• pp.569-579
• /
• 2019

A robust controller is designed based on feedback linearization and sliding mode control to damp sub-synchronous control interaction (SSCI) in doubly fed induction generator (DFIG) wind power plants (WPPs) interfaced with the grid. A feedback-linearized sliding mode controller (FLSMC) is developed for the rotor-side converter (RSC) through feedback linearization, design of the sliding mode controller, and parameter tuning with the use of particle swarm optimization. A series-compensated 100-MW DFIG WPP is adopted in simulation to evaluate the effectiveness of the designed FLSMC at different compensation degrees and wind speeds. The performance of the designed controller in damping SSCI is compared with proportional-integral controller and conventional sub-synchronous resonance damping controller. Besides the better damping capability, the proposed FLSMC enhances robustness of the system under parameter variations.

• Proceedings of the KIPE Conference
• /
• 2020.08a
• /
• pp.326-327
• /
• 2020

본 논문은 비대칭 모듈형 멀티레벨 토폴로지를 이용한 컨버터 기반 발전원의 실계통 연계에 대한 실시간 시뮬레이터 모의를 수행하였다. 비대칭 모듈형 멀티레벨 컨버터를 구성하는 6개의 암은 직렬로 연결된 다수의 하프브릿지와 풀브릿지 서브모듈로 구성되어 있으며, 각각의 서브모듈을 서로 다른 전압으로 제어하여 출력품질을 극대화 할 수 있다. 본 실험에서 사용된 실계통 및 비대칭 모듈형 멀티레벨 컨버터는 Real-Time Digital Simulator (RTDS)의 RSCAD를 이용하여 모델링 하였으며, 해당 계통 내 컨버터 기반 발전원들의 응답을 결과로 다룰 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.3
• /
• pp.1265-1274
• /
• 2018

This paper proposes a virtual flux (VF) and positive-sequence power based control strategy to improve the performance of grid-interfaced three-phase voltage source converters against unbalanced and distorted grid conditions. By using a second-order generalized integrator (SOGI) based VF observer, the proposed strategy achieves an AC voltage sensorless and grid frequency adaptive control. Aiming to realize a balanced sinusoidal line current operation, the fundamental positive-sequence component based instantaneous power is utilized as the control variable. Moreover, the fundamental negative-sequence VF feedforward and the harmonic attenuation ability of a sequence component generator are employed to further enhance the unbalance regulation ability and the harmonic tolerance of line currents, respectively. Finally, the proposed scheme is completed by combining the foregoing two elements with a predictive direct power control (PDPC). In order to verify the feasibility and validity of the proposed SOGI-VFPDPC, the scenarios of unbalanced voltage dip, higher harmonic distortion and grid frequency deviation are investigated in simulation and experimental studies. The corresponding results demonstrate that the proposed strategy ensures a balanced sinusoidal line current operation with excellent steady-state and transient behaviors under general grid conditions.

• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.786-792
• /
• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.11-14
• /
• 2003

A silicon based OELD driving circuit that has a new type of column driving method is proposed to reduce the driving circuit area. In comparison with the conventional method, latches in each column are removed and one DAC (digital-to-analog converter) drives several column lines. To make the DAC operate during a specific period for the low power consumption, a simple DESG (DAC Enable Signal Generator) circuit was devised and confirmed by the simulation.