• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.726-742
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• 2000

A novel rte control algorithm consisting of two major components, i.e. a variable encoding frame rate method and a hybrid DCT/wavelet I-frame coding scheme, is proposed in this work for low bit rate video coding. Most existing rate control algorithms for low bit rate video focus on bit allocation at the macroblock level under a constant frame rate assumption. The proposed rate control algorithm is able to adjust the encoding frame rate at the expense of tolerable time-delay. Furthermore, an R-D optimized hybrid DCT/wavelet scheme is used for effective I-frame coding. The new rate-control algorithm attempts to achieve a good balance between spatial quality and temporal quality to enhance the overall human perceptual quality at low bit rates. It is demonstrated that the rate control algorithm achieves higher coding efficiency at low bit rates with a low additional computational cost. The variable frame rate method and hybrid I-frame coding scheme are compatible with the bi stream structure of H.263+.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.174-178
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet (PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator, the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF, resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• Journal of Power Electronics
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• v.1 no.2
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• pp.88-98
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet(PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF., resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• Korean Journal of Applied Biomechanics
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• v.13 no.1
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• pp.1-12
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• 2003

The purpose of this study was to design the method of 3D space calibration to reduce RMSE by statistical analysis when using the DLT algorithm and control frame. Control frame for 3D space calibration was consist of $1{\times}3{\times}2m$ and 162 contort points adhere to it. For calculate of 3D coordination used two methods about 2D coordination on image frame, 2D coordinate on each image frame and mean coordination. The methods of statistical analysis used one-way ANOVA and T-test. Significant level was ${\alpha}=.05$. The compose of methods for reduce RMSE were as follow. 1. Use the control frame composed of 24-44 control points arranged equally. 2. When photographing, locate control frame to center of image plane(image frame) o. use the lens of a few distortion. 3. When calculate of 3D coordination, use mean of 2D coordinate obtainable from all image frames.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.25-28
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• 2002

This paper presents variable bit rate(VBR) rate control scheme based on MPEG-4 VM8 rate control scheme. An initial Q searching method provides more accurate bit allocation for the first frame. A frame skipping and RD Model update scheme when coded frame quality is too low or high prevents image quality fluctuation.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.8
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• pp.109-118
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• 1994

We proposed new field/frame mode selection quantization and buffer control strategy for interlaced digital HDTV image coding system. The field/frame mode selection is performed based on the mean square error and number of generated bits for each superblock. The quantization factor for each superblock is determined by the characteristics of human visual system and buffer status. The statistical characteristics of the number of generated bits for basis block and the prediction of buffer status are used for buffer control. Simulation results show that the proposed field/frame mode selection and rate buffer control. Simulation results show that the proposed field/frame mode selection and rate buffer control strategy have good subjective image quality and have stable buffer status.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.295-296
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• 2006

We developed wire frame drive unit based on SMA for the 3D Shape display. Our basic concept is wire frame combination connected with a chain form which can create various shapes and it compared with pin array mechanism which is not able to display mushroom shape. It imitates antagonist mechanism of human musculoskeletal system. we create similar motion using repair-relaxation mechanism and locking mechanism by SMA. Therefore, in this paper, we propose SMA control solution for actuating repair-relaxation mechanism and locking mechanism. In our control system. we use optical sensor and quantitative angle between wire frames for closed loop control. And we supply amplified current for SMA by circuit composed of transistor and apply PWM signal to circuit for efficient control. So, wire frame drive unit enable diversity angle control based on sensor data. And then combination of wire frame drive units will create various objects.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.199-206
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• 2016

This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the data frame configuration. To add a routing control signal, called the "labeling signal" in this paper, to the data frame, we use a frequency modulation technique on the transmitted frame. This means you need not change the data frame when you transmit additional signals. Using a prototype system comprising a field-programmable gate array and discrete elements, we investigate the system performance and devise a method to achieve high resolution. A three-channel routing control for a 10 Gb/s data frame was achieved, which confirms the advantages of the proposed system.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.61-70
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• 2011

IEEE 802.11 wireless network supports control frames like RTS/CTS(Request To Send / Clear To Send). Because they is defend to frame collection problems. It helps to solve the frame collection problem but decreases the throughput rate. Also, control frame makes False Node Problem. This problem is makes to other wireless nodes don't work and don't find channels in the same cell and near cells. We proposed a reformed new control frame for efficiency throughput rate and solution of False Node Problem. New control frame is to have added to 4 bytes of channel detection ability at the RTS frames. Channel detection ability supported to check channel at the wireless node start to transmit data frame, We expect that channel detection ability make prevent False Node Problem for increase to access number to channel. We perform comparative analysis in terms of delay(sec) and load(bits/sec) with reform RTS/CTS method which proves the efficiency of the proposed method.