• Journal of information and communication convergence engineering
• /
• 제11권4호
• /
• pp.282-287
• /
• 2013

A real-time digital holographic display is the core technology for the next-generation 3DTV. Holographic display requires a considerably large amount of calculation. If generating a large number of digital holograms is intended, the amount of calculation and the time required increase exponentially. This is a significant obstacle in a real-time hologram service. This paper proposes an algorithm that increases the speed of generating a Fresnel hologram by using a recursive addition operation covering the entire coordinate array of a digital hologram. The 3D object designed to calculate the digital hologram uses a depth-map image produced by computer graphics. The proposed algorithm is a technique that performs the computer-generated holography (CGH) operation with only recursive addition of all of the hologram's coordinates by analyzing the regularity between the 3D object and the digital hologram coordinates. The experimental results show that the proposed algorithm increases the operation speed by 70% over the technique using the conventional CGH equation and by more than 30% over the previously proposed recursive technique.

• 디지털산업정보학회논문지
• /
• 제9권1호
• /
• pp.129-139
• /
• 2013

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

• Current Optics and Photonics
• /
• 제6권1호
• /
• pp.51-59
• /
• 2022

Holographic display technology is one of the promising 3D display technologies. However, the large amount of computation time required to generate computer-generated holograms (CGH) is a major obstacle to the commercialization of digital hologram. In various systems such as multi-depth head-up-displays with hologram contents, it is important to transmit hologram data in real time. In this paper, we propose a rapid CGH computation method by applying an arraying of a down-scaled hologram with the multiplication of a shifted concave lens function array. Compared to conventional angular spectrum method (ASM) calculation, we achieved about 39 times faster calculation speed for 3840 × 2160 pixel CGH calculation. Through the numerical investigation and experiments, we verified the degradation of reconstructed hologram image quality made by the proposed method is not so much compared to conventional ASM.

• 제어로봇시스템학회논문지
• /
• 제15권5호
• /
• pp.548-554
• /
• 2009

We propose an automatic inspection system for hologram with multiple patterns. The system hardware consists of illuminations, camera, and vision processor. Multiple illuminations using LEDs are arranged in different directions to acquire each image of patterns. The system software consists of pre-processing, pattern generation, and pattern matching. The acquired images of input hologram are compared with their reference patterns by developed matching algorithm. To compensate for the positioning error of input hologram, reference patterns of hologram for different position should be generated in on-line. We apply a frequency transformation based CGH(computer-generated hologram) method to generate reference images. For the fast pattern matching, we also apply the matching method in the frequency domain. Experimental results for hologram of Korean currency are then presented to verify the usefulness of proposed system.

• 한국통신학회논문지
• /
• 제33권5C호
• /
• pp.386-394
• /
• 2008

디지털 홀로그래픽 비디오 시스템을 제작하기 위해서는 디지털 홀로그램을 가능한 빠르게 생성하는 것이 중요하다. 본 논문에서는 디지털 홀로그램의 전체 좌표를 대상으로 반복적인 가산 연산을 이용하여 Fresnel 홀로그램의 생성 속도를 높이는 알고리듬을 제안한다. 디지털 홀로그램을 계산하기 위한 3차원 객체는 컴퓨터 그래픽(computer graphic, CG)으로 제작한 깊이영상(depth-map image)을 이용하였다. 본 논문에서 제안하는 알고리듬은 부동소수점 형식의 반복가산기법을 이용하여 디지털 홀로그램의 위상을 고속으로 계산하는 기법이다. 실험결과 제안한 알고리듬은 일반적인 CGH 수식을 이용한 기법의 70%, [3]에서 제안한 기법보다 30%이상 연산속도가 빨라졌다.