• 제목/요약/키워드: Computer system architecture

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JarBot: Automated Java Libraries Suggestion in JAR Archives Format for a given Software Architecture

  • P. Pirapuraj;Indika Perera
    • International Journal of Computer Science & Network Security
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    • v.24 no.5
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    • pp.191-197
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    • 2024
  • Software reuse gives the meaning for rapid software development and the quality of the software. Most of the Java components/libraries open-source are available only in Java Archive (JAR) file format. When a software design enters into the development process, the developer needs to select necessary JAR files manually via analyzing the given software architecture and related JAR files. This paper proposes an automated approach, JarBot, to suggest all the necessary JAR files for given software architecture in the development process. All related JAR files will be downloaded from the internet based on the extracted information from the given software architecture (class diagram). Class names, method names, and attribute names will be extracted from the downloaded JAR files and matched with the information extracted from the given software architecture to identify the most relevant JAR files. For the result and evaluation of the proposed system, 05 software design was developed for 05 well-completed software project from GitHub. The proposed system suggested more than 95% of the JAR files among expected JAR files for the given 05 software design. The result indicated that the proposed system is suggesting almost all the necessary JAR files.

Sensor Network Implementation of using Embedded Web Sever

  • Lee Jeong Gi;Shin Myung Souk;Park Do Joon;Lee Cheol Seung;Kim Choong Woon;Lee Joon
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.532-535
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    • 2004
  • Architecture generation is the first step in the design of software systems. Most of the qualities that the final software system possesses are usually decided at the architecture development stage itself. Thus, if the final system should be usable, testable, secure, high performance, mobile and adaptable, then these qualities or non­functional requirements should be engineered into the architecture itself. In particular, adaptability is emerging as an important attribute required by almost all software systems. The machinery and tools in the remote site surveillance and connects intelligence information machinery and tools at Internet. We need the server which uses different embedded operating system to become private use. With the progress of information-oriented society, many device with advanced technologies invented by many companies. However, the current firmware technologies have many problems to meet such high level of new technologies. In this paper, we have successfully ported linux on an embedded system, which is based on intel StrongARM SA-1 1 10 processor, then written several network modules for internet-based network devices.

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IoT data analytics architecture for smart healthcare using RFID and WSN

  • Ogur, Nur Banu;Al-Hubaishi, Mohammed;Ceken, Celal
    • ETRI Journal
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    • v.44 no.1
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    • pp.135-146
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    • 2022
  • The importance of big data analytics has become apparent with the increasing volume of data on the Internet. The amount of data will increase even more with the widespread use of Internet of Things (IoT). One of the most important application areas of the IoT is healthcare. This study introduces new real-time data analytics architecture for an IoT-based smart healthcare system, which consists of a wireless sensor network and a radio-frequency identification technology in a vertical domain. The proposed platform also includes high-performance data analytics tools, such as Kafka, Spark, MongoDB, and NodeJS, in a horizontal domain. To investigate the performance of the system developed, a diagnosis of Wolff-Parkinson-White syndrome by logistic regression is discussed. The results show that the proposed IoT data analytics system can successfully process health data in real-time with an accuracy rate of 95% and it can handle large volumes of data. The developed system also communicates with a riverbed modeler using Transmission Control Protocol (TCP) to model any IoT-enabling technology. Therefore, the proposed architecture can be used as a time-saving experimental environment for any IoT-based system.

RealToon service architecture with multilayer (멀티레이어 기반 리얼툰 서비스 아키텍처 제안)

  • Kwak, Ji-Hye;Park, Min-Ji;Kim, Ye-Sul;Lee, Seung-Hyung;Chae, Ok-Sam
    • Proceedings of the Korean Information Science Society Conference
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    • 2012.06d
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    • pp.146-148
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    • 2012
  • 본 논문에서는 최근 이슈가 되고 있는 문화 컨텐츠인 WebToon 의 단순한 표현력을 보완하고 정적인 카툰이 아닌 동적인 카툰을 제공하는 서비스에 대해 기술한다. Background, Object, Particle 3 개의 Multi Layer 를 기반으로 중력가속도, 모멘트연산을 이용한 물리엔진이 적용된 Particle system 을 사용하여 컨텐츠에 동적인 효과를 나타내준다. 컨텐츠 제작자가 PC Tool 에서 작업한 컨텐츠를 리얼툰 서비스를 통하여 관리하고, Application 을 통하여 독자에게 제공하는 서비스에 대한 Architecture 를 제안한다.

Design of a Multi-Agent System Architecture for Implementing CPFR (CPFR 구현을 위한 다중 에이전트 시스템 구조설계)

  • Kim, Chang-Ouk;Kim, Sun-II;Yoon, Jung-Wook;Park, Yun-Sun
    • Journal of Korean Institute of Industrial Engineers
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    • v.30 no.1
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    • pp.1-10
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    • 2004
  • Advance in Internet technology has changed traditional production planning and control methods. In particular, collaborations between participants in supply chains are being increasingly addressed in industry for enhancing chain-wide productivity. A representative paradigm that emphasizes collaboration in production planning and control is CPFR(Collaborative Planning, Forecasting and Replenishment). In this paper, we present a multi-agent system architecture that supports the collaborations specified in CPFR. The multi-agent system architecture consists of event manager, data view agent, business rule agent, and collaboration agent. The collaboration agent systematically controls negotiation between supplier and buyer with the aid of collaboration protocol and blackboard. The multi-agent system has been implemented with EJB(Enterprise Java Beans).

A System Level Network-on-chip Model with MLDesigner

  • Agarwal, Ankur;Shankar, Rabi;Pandya, A.S.;Lho, Young-Uhg
    • Journal of information and communication convergence engineering
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    • v.6 no.2
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    • pp.122-128
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    • 2008
  • Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

A Cycle-Accurate Simulation Environment for Shader Architecture (쉐이더 구조를 위한 마이크로 아키텍쳐 시뮬레이션 환경)

  • Han Sang-Won;Lee Won-Jong;Han Tack-Don
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.06a
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    • pp.196-198
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    • 2006
  • Shader architecture is one of the fastest growing fields in the ever advancing 3D graphics, and massive amounts of Ideas and technologies are being introduced to the market continuously. In this paper, we present a flexible cycle-accurate simulation environment to accelerate and alleviate the process of developing and verifying these ideas and technologies. Combination of 3D graphics API and hardware simulator allows OpenGL applications to be emulated off-the-shelf for a given shader micro-architecture. Easily modified parameters allow the simulation environment to be tailored to specific demands or requirements.

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An Architecture for Efficient Intrusion Detection System of Abnormal Traffic (비정상 트래픽 상황에서 효율적 침입 탐지 시스템(EIDS) 구조 연구)

  • Kwon, Young-Jae;Lee, Du-Man;Yim, Hong-Bin;Jung, Jae-Il
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.207-208
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    • 2006
  • Intrusion detection technology is highlighted in order to establish a safe information-oriented environment. Intrusion detection system can be categorized into anomaly detection and misuse detection according to intrusion detection pattern. In this paper, we propose an architecture to make up for the defect of conventional anomaly intrusion detection. This architecture reduces additional resource consumption and cost by placing the agent in the strategic location in Internet.

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Research of the Architecture of Indoor Navigation System based on Mobile Device (모바일 기기에서의 실내 네비게이션 시스템 아키텍쳐의 연구)

  • Jin, Liang;Zhou, Jian;Lee, Yeon;Bae, Hae-Young
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2012.01a
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    • pp.173-175
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    • 2012
  • To spread the incredible experience of wandering around a building, we propose the architecture of indoor navigation system based on inter-floor. Firstly, we combine trilateration method with Fingerprint Positioning Algorithm for positioning and Dijkstra Algorithm for calculating paths. Then the system can get the user's current locations and provide relevant paths according to the user's choice. Moreover, it can also provide the navigation path which takes the inter-floor information into consideration. It breaks the traditional navigation based on planar graph and has abundant business value.

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Design and Performance Analysis of the H/V-bus Parallel Computer (H/V-버스 병렬컴퓨터의 설계 및 성능 분석)

  • 김종현
    • Journal of the Korea Society for Simulation
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    • v.3 no.1
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    • pp.29-42
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    • 1994
  • The architecture of a MIMD-type parallel computer system is specified: a simulator is developed to support design and evaluation of systems based on the architecture: and conducted with the simulator to evaluate system performance. The horizontal/vertical-bus(H/V-bus) system architecture provides an NxN array of processing elements which communicate with each other through a network of N horizontal buses and N vertical buses. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution in simulating the IPC mechanism. Parameters provide the user with independent control of system size, PE speed and IPC mechanism speed. Results generated by the simulator include execution times, PE utilizations, queue lengths, and other data. The simulator is used to study system performance when a partial differential equation is solved by parallel Gauss-Seidel method. For comparisons, the benchmark is also executed on a single-bus system simulator that is derived from the H/V-bus system simulator. The benchmark is also solved on a single PE to obtain data for computing speedups. An extensive analysis of results is presented.

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