• IEIE Transactions on Smart Processing and Computing
• /
• 제4권3호
• /
• pp.169-172
• /
• 2015

Dalvik is a virtual machine (VM) that is designed to run Java-based Android applications. A trace-based just-in-time (JIT) compilation technique is currently employed to improve performance of the Dalvik VM. However, due to runtime compilation overhead, the trace-based JIT compiler provides only a few simple optimizations. Moreover, because each trace contains only a few instructions, the trace-based JIT compiler inherently exploits fewer optimization and parallelization opportunities than a method-based JIT compiler that compiles method-by-method. So we propose a new method-based JIT compiler, named DEX2C, in order to improve performance by finding more opportunities for both optimization and parallelization in Android applications. We employ C code as an intermediate product in order to find more optimization opportunities by using the GNU C Compiler (GCC), and we will detect parallelism by using the Intel C/C++ parallel compiler and the AESOP compiler in our future work. In this paper, we introduce our DEX2C compiler, which dynamically translates Dalvik bytecodes (DEX) into C code with method granularity. We also describe a new method-based JIT interface in the Dalvik VM for the DEX2C compiler. Our experiment results show that our compiler and its interface achieve significant performance improvement by up to 15.2 times and 3.7 times on average, in Element Benchmark, and up to 2.8 times for FFT in Smartbench.

• 정보처리학회논문지A
• /
• 제18A권3호
• /
• pp.109-114
• /
• 2011

IR(Intermediate Representation) 최적화 과정은 컴파일러 back-end의 중요한 부분으로서 sub-expression elimination, dead code elimination 등 최적화 기법들을 사용한다. 하지만 IR 최적화 단계에서 생기는 에러들을 검출하고 디버깅하는데 많은 어려움이 있다. 그 첫 번째 이유로는 컴파일 된 어셈블리 코드를 해독하여 에러를 체크하기 어렵고 두 번째로는 IR 최적화 단계에서 에러가 생겼는지 결정 짓기 어렵기 때문이다. 이런 이유들로 인하여, 우리는 C 레벨에서 IR 코드변환 무결점 여부를 체크하기 위한 기법들에 관한 연구를 진행하여 왔다. 우리는 MeCC(Memory Comparison-based Clone) 탐색기를 기반으로 하여, 최적화하기 전 IR코드와 최적화 한 후의 IR코드를 각각 C코드로 다시 변환한 뒤, 이 두 개의 C코드를 MeCC의 입력으로 주고, 결과의 일치 여부를 확인하는 방법을 사용한다. 하지만 MeCC가 완벽한 결과를 알려주지 않기 때문에, 우리는 각 IR 최적화 기법마다의 특징에 대한 정보를 사전에 처리해서 그 결과의 정확도를 높였다. 이 논문에서는 dead code elimination, instruction scheduling 및 common sub-expression elimination 등 최적화 기법들을 이용한 변환 코드들을 예시로 실험하여 최종적으로 MeCC에서의 C 레벨 코드의 정확한 에러 체크 동작여부를 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제6권4호
• /
• pp.234-239
• /
• 2006

In the past decade, several tools have been developed to automate the floating-point to fixed-point conversion for DSP systems. In the conversion process, a number of scaling shifts are introduced, and they inevitably alter the original code sequence. Recently, we have observed that a compiler can often be adversely affected by this alteration, and consequently fails to generate efficient machine code for its target processor. In this paper, we present an optimization technique that safely migrates scaling shifts to other places within the code so that the compiler can produce better-quality code. We consider our technique to be safe in that it does not introduce new overflows, yet preserving the original SQNR. The experiments on a commercial fixed-point DSP processor exhibit that our technique is effective enough to achieve tangible improvement on code size and speed for a set of benchmarks.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2003년도 ICCAS
• /
• pp.1349-1353
• /
• 2003

CEMTool is a command style design and analyzing package for scientific and technological algorithm and a matrix based computation language. In this paper, we present a compiler based approach to the implementation of the command mode generalized PDE solver in CEMTool. In contrast to the existing MATLAB PDE Toolbox, our proposed FEM package can deal with the combination of the reserved words such as "laplace" and "convect". Also, we can assign the border lines and the boundary conditions in a very easy way. With the introduction of the lexical analyzer and the parser, our FEM toolbox can handle the general boundary condition and the various PDEs represented by the combination of equations. That is why we need not classify PDE as elliptic, hyperbolic, parabolic equations. Consequently, with our new FEM toolbox, we can overcome some disadvantages of the existing MATLAB PDE Toolbox.

• 대한임베디드공학회논문지
• /
• 제6권6호
• /
• pp.345-359
• /
• 2011

In high performance embedded systems, the use of multiple on-chip memories is an essential architectural feature for exploiting inherent parallelism in multimedia applications. This feature allows multiple data accesses to be executed in parallel. However, it remains difficult to effectively exploit of multiple on-chip memories. The successful use of this architecture strongly depends on how to efficiently detect and exploit memory parallelism in target applications. In this paper, we propose a technique based on a linear array access descriptor [1], which is generated from profiled data, to detect and exploit memory parallelism. The proposed technique tackles an array reorganization problem to maximize memory parallelism in multimedia applications. We present preliminary experiments applying the proposed technique onto a representative coarse grained reconfigurable array processor (CGRA) with multimedia kernel codes. Our experimental results demonstrate that our technique optimizes data placement by putting independent data on separate storage. The results exhibit 9.8% higher performance on average compared to the existing method.

• 한국IT서비스학회지
• /
• 제10권3호
• /
• pp.167-177
• /
• 2011

Code obfuscation is a technique that protects the abstract data contained in a program from malicious reverse engineering and various obfuscation methods have been proposed for obfuscating intention. As the abstract data of control flow about programs is important to clearly understand whole program, many control flow obfuscation transformations have been introduced. Generally, inlining is a compiler optimization which improves the performance of programs by reducing the overhead of calling invocation. In code obfuscation, inlining is used to protect the abstract data of control flow. In this paper, we define new control flow complexity metric based on entropy theory and N-Scope metric, and then apply genetic algorithm to obtain optimal inlining results, based on the defined metric.

• 한국컴퓨터정보학회논문지
• /
• 제10권3호
• /
• pp.75-88
• /
• 2005

본 논문에서는 원격으로 제어 가능한 실시간 시스템에서 발생 가능한 악의적인 코드 삽입에 의한 보안 공격을 방지할 수 있는 방법을 제안한다. 제안하는 방법은 원격으로 제어 코드를 전달하여 시스템을 업그레이드하는 경우 전달된 제어 코드의 안전성을 실행 전에 분석하는 방법으로서 정적 프로그램 분석 방법을 이용한다. 제안하는 분석 방법을 구현한 도구를 컴파일러 내에 삽입하여 실제 원격으로 소프트웨어 업그레이드가 가능한 실시간 시스템 환경에 적용하여 효용성을 검증하였다.

• 한국정보처리학회논문지
• /
• 제6권2호
• /
• pp.307-314
• /
• 1999

본 논문에서는 순차 언어로 작성된 프로그램을 '병렬화'와 지역성 향상'을 목적으로 변형시키는 최적화 기법에 대해서 논의한다. 의존성과 지역성을 고려하여 순차 프로그램의 루프 구조를 분석하고, 루프 분산과 루프 병합 기법을 적용하여 프로그램을 변형시킨다. 이 변형된 프로그램은 쉽게 '굵은 단위'의 병렬성과 지역성이 향상된 형태의 쓰레드 프로그램으로 표현될 수 있다. 따라서 이 변형 기법은 최적화/자동병렬화 컴파일러 구현에 유용하게 응용될 수 있다. 4개의 SPARC 프로세서를 장착한 Solaris 시스템에서 이 기법을 SPEC95 프로그램에 적용하여 시험한 결과 순차프로그램과는 20∼62%, 기존의 SUIF 병렬화 컴파일러와는 3∼12% 정도의 수행시간이 개선되는 효과를 얻게 되었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.351-355
• /
• 1999

The amount of data stored, processed and transmitted in the multi-media systems has been growing very fast, especially for the image data. For example, it takes 0.75Mbytes to store 512 12 pixels of 24-bit color image. A video signal with 30 frames per second will require 22.5Mbytes of storage space. To solve this problem, we need a good image compression technique. Recently, many researches on the image compression technique based on the wavelet transform are being pursued to overcome the problems of traditional JPEG. This paper describes the architecture and design of two-dimensional wavelet transform circuit. To keep the sire of the circuit small, we tried to minimize the internal storage space by using external SDRAM. This circuit was designed in Verilog-HDL, synthesized using Design Compiler and verified using Verilog-XL.

• 한국시뮬레이션학회논문지
• /
• 제12권2호
• /
• pp.45-53
• /
• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.