• Journal of Power Electronics
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• 제17권3호
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• pp.641-652
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• 2017

This paper proposes a cost-effective topology to drive a three-phase open-end load based on a five-leg indirect matrix converter (IMC) and a space vector modulation (SVM) method. By sharing an inverter leg with two load terminals, the proposed topology can reduce the number of power switches when compared to topologies based on a direct matrix converter or a six-leg IMC. The new SVM method uses only the active vectors that do not produce common-mode voltage (CMV), which results in zero CMV across the load phase and significantly reduces the peak value of the CMV at the load terminal. Furthermore, the proposed drive system can increase the voltage transfer ratio up to 1.5 and provide a superior performance in terms of an output line-to-line voltage with a three-level pulse-width modulation waveform. Simulation and experimental results are given to verify the effectiveness of the proposed topology and the new SVM method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.36-42
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• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• 전력전자학회논문지
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• 제27권2호
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• pp.85-91
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• 2022

This study proposes a high efficiency bridgeless Power Factor Correction (PFC) converter with improved common mode noise characteristics. Conventional PFC has limitations due to low efficiency and enlarged heat sink from considerable conduction loss of bridge diode. By applying a Common Mode (CM) coupled inductor, the proposed bridgeless PFC converter generates less conduction loss as only a small magnetizing current of the CM coupled inductor flows through the input diode, thereby reducing or removing heat sink. The input diode is alternately conducted every half cycle of 60 Hz AC input voltage while a negative node of AC input voltage is always connected to the ground, thus improving common mode noise characteristics. With the aim to improve switching loss and reverse recovery of output diode, the proposed circuit employs Critical Conduction Mode (CrM) operation and it features a simple Zero Current Detection (ZCD) circuit for the CrM. In addition, the input current sensing is possible with the shunt resistor instead of the expensive current sensor. Experimental results through 480 W prototype are presented to verify the validity of the proposed circuit.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.638-642
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• 2005

This paper proposes a modified space-vector pulse width modulation (PWM) strategy which can restrict the common-mode voltage for three-phase to three-phase matrix converter and still keep sinusoidal input and output waveforms and unity power factor at the input side. The proposed control method has been developed based on contributing the appropriate space vectors instead of using zero space vectors. The advantages of this proposed method is to reduce the peak value of common-mode voltage to 42% beside the lower high harmonic components as compared to the conventional SVM method. Hence, the new table is also presented with the new space vector rearrangement. Furthermore, the voltage transfer ratio is unaffected by the proposed method. A simulation of the overall system has been carried out to validate the advantages of the proposed method.

• Journal of Power Electronics
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• 제19권4호
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• pp.907-921
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• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.487-488
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• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• 대한의용생체공학회:의공학회지
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• 제39권2호
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• pp.103-108
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• 2018

This study reviews the common-mode noise model of indirect-contact ECG measurement which uses capacitive electrode and capacitive ground, and shows the reason of the large common-mode noise in indirect-contact ECG. And then, this study shows driven-right-leg ground in indirect-contact ECG measurement, and reviews how the driven-right-leg ground reduces the common-mode noise. This study then analyzes the relation between the effective area of the indirect-contact ground and the gain of the driven-right-leg circuit. This study introduces the output voltage saturation of the driven-right-leg circuit, which occurs frequently in indirect-contact ECG measurement with the condition of the high ground impedance. This study then shows the effect of the driven-right-leg circuit saturation on the common-mode noise.

• Journal of Power Electronics
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• 제16권3호
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• pp.1236-1243
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• 2016

This paper presents the analysis and design of an active electromagnetic interference (EMI) filter (AEF) for the common-mode (CM) noise reduction of switching power converters. The features of the several types of AEFs are discussed and compared in terms of implementation. The feed-forward AEF with a voltage-sensing and voltage-cancellation (VSVC) structure is implemented for an LLC resonant converter to replace a multiple-stage passive EMI filter and thereby reduce CM noise. The characteristics and performance of the VSVC-type AEF are investigated through theoretical and experimental works.

• 전력전자학회논문지
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• 제27권5호
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• pp.446-454
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• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• Journal of Power Electronics
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• 제18권1호
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.