• 한국컴퓨터정보학회논문지
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• 제18권7호
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• pp.47-55
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• 2013

임베디드 시스템에 구현되는 대부분의 어플리케이션들은 MCU가 제공하는 타이머를 사용한다. 타이머 사용의 목적은 실시간 운영체제의 소프트웨어 타이머 구현에서부터 센서의 워밍업이나 처리의 경과 시간 측정 등에 이르기까지 다양하다. 이들어플리케이션들이의시간측정은그길이뿐만아니라정밀도측면에서수us~수백ms 정도로 그 범위가 다양하다. 이 논문에서는 타이머를 활용하는 과정에서 클록 펄스 비동기화로 인해 발생할 수 있는 오차 요인을 분석하고, 이러한 오차를 감소시키기 위한 타이머 클록 펄스 동기화 방안을 제시한다. 실험 결과, 32768Hz의 타이머를 8 분주한 4096Hz 타이머의 경우 약 230us까지의 편차가 발생하지만, 제안된 방법을 적용하면 타이머로 인한 편차를 10us 이내로 유지할 수 있다.

• Journal of Positioning, Navigation, and Timing
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• 제12권3호
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• pp.215-228
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• 2023

The State Space Representation (SSR) method provides individual corrections for each Global Navigation Satellite System (GNSS) error components. This method can lead to less bandwidth for transmission and allows selective use of each correction. Precise Point Positioning (PPP) - Real-Time Kinematic (RTK) is one of the carrier-based precise positioning techniques using SSR correction. This technique enables high-precision positioning with a fast convergence time by providing atmospheric correction as well as satellite orbit and clock correction. Currently, the positioning service that supports PPP-RTK technology is the Quazi-Zenith Satellite System Centimeter Level Augmentation System (QZSS CLAS) in Japan. A system that provides correction for each GNSS error component, such as QZSS CLAS, requires monitoring of each error component to provide reliable correction and integrity information to the user. In this study, we conducted an analysis of the performance of residual error bounding for each error component. To assess this performance, we utilized the correction and quality indicators provided by QZSS CLAS. Performance analyses included the range domain, dispersive part, non-dispersive part, and satellite orbit/clock part. The residual root mean square (RMS) of CLAS correction for the range domain approximated 0.0369 m, and the residual RMS for both dispersive and non-dispersive components is around 0.0363 m. It has also been confirmed that the residual errors are properly bounded by the integrity parameters. However, the satellite orbit and clock part have a larger residual of about 0.6508 m, and it was confirmed that this residual was not bounded by the integrity parameters. Users who rely solely on satellite orbit and clock correction, particularly maritime users, thus should exercise caution when utilizing QZSS CLAS.

• Journal of Positioning, Navigation, and Timing
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• 제13권1호
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• pp.111-115
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• 2024

This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

• 전자공학회논문지A
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• 제33A권3호
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• pp.47-54
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• 1996

In this paper we propose a new timing recovery method by means of utilizing service data filling rate instead of timing information of transmitter. A proposed algorithm controls the phase locked loop in the opposite direction ot data filling rate of FIFO in receiver, and it is based on the fact that average of cell jitters is zero. The proposed method is simple compared with timing information method of transmitter. It can be utilized for timing recovery in synchronous digital hierarchy as well as in plesiochronous digial hierarchy without common reference clocks in end-to-end erminals. We implement the interactive video communication system and test the proposed algorithm. As a result, we hav econfirmed that it yields good perfomrnces in terms of jitters characteristics and hardware complexity.

• 사물인터넷융복합논문지
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• 제1권1호
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• pp.33-38
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• 2015

하드웨어는 다양한 구조로 개발되고, 모듈들에 대한 시간 시뮬레이션을 할 때 각 클럭 사이클에 사용되는 변수들의 값을 확인할 필요가 있다. 본 논문은 224비트 ECDSA 하드웨어를 개발하면서 하드웨어 모듈의 시간 시뮬레이션을 위한 테스트 벡터를 제공하는 소프트웨어 생성기를 소개한다. 테스트 벡터는 GUI 형태와 텍스트 파일 형태로 제공된다.

• 전자공학회논문지B
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• 제32B권12호
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• 한국통신학회논문지
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• 제21권2호
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• pp.417-426
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• 1996

The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.121-124
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• 2002

The IEEE 802.lla PLCP H/W for Processing efficiently control message between MAC and PHY is designed. Slate machine and clock control according to rate is designed and timing diagram is verified on the FPGA simulation environment.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2009년도 정보통신설비 학술대회
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• pp.275-280
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• 2009

Femtocells are viewed as a promising option for mobile operators to improve coverage and provide high-data-rate services in a cost-effective manner Femtocells can be used to serve indoor users, resulting in a powerful solution for ubiquitous indoor and outdoor coverage. TThe frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) forapplications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the femtocell. But, the GPS has some problem to be used at the femtocell, because it is difficult to set-up, depends on the satellite condition, and very expensive. The IEEE 1588 specification provides a low-cost means for clock synchronisation over a broadband Internet connection. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. However, the timing synchronization over packet switched networks is a difficult task because packet networks introduce large and highly variable packet delays. This paper proposes an enhanced filter algorithm to reduce ths packet delay variation effects and maintain ToP slave clock synchronization performance. The results are presented to demonstrate in the intra-networks and show the improved performance case when the efficient ToP filter algorithm is applied.