• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.540-547
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• 2004

In this paper, a current - mode class D(CMCD) power amplifier over 70 % power added efficiency at 900 ㎒ is designed and implemented. Based on push-pull class B structure, main power loss due to charge and discharge of output capacitance in switching mode power amplifier is minimized by applying a parallel harmonic control circuit. Experimental CMCD amplifier with 73 % power added efficiency at 3.2 W and 72 % power added efficiency at 5 W are achieved respectively. In addition a characteristic of switching mode power amplifier whose output power is proportional to magnitude of U power is verified.

• Journal of Korea Multimedia Society
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• v.21 no.9
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• pp.1068-1075
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• 2018

We propose a method for driving loudspeakers from class D audio power amplifiers in current mode, instead of in conventional voltage mode, which was impossible with the feedback circuitry. Unlike analog audio amplifiers, Class D audio power amplifiers have signal delay between the input and output signals, which makes it difficult to apply the feedback circuitry for current-mode driving. The idea of the pre-distortion scheme used for the compensation of the non-linearity of RF power amplifiers is adapted to remedy the impedance variation effect of the loudspeakers for current driving. The method uses the speaker model for the pre-distorter to compensate for the speaker impedance variation with frequency. The simulation and test results confirms the validity of the proposed method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1060-1068
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• 2011

In this paper, Current-Mode Class-D(CMCD) RF Power Amplifier(PA) is designed and implemented at 900 MHz. Conventional CMCD PA has output parallel resonator to reconstruct a fundamental frequency component of the output signal. However the resonator can be removed by connecting inverse class-F PAs because even-harmonic components can be removed by CMCD PA's push-pull structure. Using load-pull, inverse class-F PA with GaN transistors is designed, and CMCD PA with the inverse class-F PA is implemented. The CMCD PA has 64.5 % drain efficiency, 34.2 dBm output power. Comparing with the drain efficiency of a CMCD PA with parallel resonator, the CMCD with the inverse class-F technology has 13.6 % improved drain efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.624-631
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• 2012

This paper presents a high-efficiency current mode class-D(CMCD) power amplifier for the 13.56 MHz band using a Guanella's 1:1 transmission-line transformer and filtering circuits at the output network. The second and third s are filtered out in the load network of the class-D amplifier. The implemented CMCD power amplifier exhibited a power gain of 13.4 dB and a high power-added efficiency(PAE) of 84.6 % at an output power of 44.4 dBm using the 13.56 MHz CW input signal. The second and third distortion levels were -50.3 dBc and -46.4 dBc at the same output power level, respectively.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.166-171
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• 2019

This paper has designed a current mode class D power amplifier to increase the transmission efficiency of a 6.78 MHz wireless power transfer (WPT) transmitter and to ensure stable characteristics even when the transmitting and receiving coil intervals change. By reducing the loss due to the parasitic capacitor component of the transistor, which limits the theoretical efficiency of the linear amplifier, this research has improved the efficiency of the power amplifier. The circuit design simulator was used to design the high efficiency amplifier, and the power output and efficiency characteristics according to the load impedance change have been simulated and verified. In the simulation, 42.1 dBm output and 95% efficiency was designed at DC bias 30 V. The power amplifier was fabricated and showed 91% efficiency at the output of 42.1 dBm (16 W). The transmitting and receiving coils were fabricated for wireless power transfer of the drone, and the maximum power added efficiency was 88% and the output power was $42.1dBm{\pm}1.7dB$ according to the load change causing from the coil intervals.

• ETRI Journal
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• v.34 no.6
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• Journal of electromagnetic engineering and science
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• v.14 no.3
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• pp.284-292
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• 2014

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.82-90
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• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.48-56
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• 2011

Novel class-A bipolar current conveyor($CCII{\pm}$) with differential current output and its application to output current controllable CCII+ for electronic tuning systems are designed. The $CCII{\pm}$ is consists of conventional CCII+ and complementary cross current sources. The CCII+ with controllable the output current consists of the $CCII{\pm}$ and a current gain amplifier with single-ended current output. The simulation result shows that the $CCII{\pm}$ has current input impedance of $1.9{\Omega}$ and a good linearity for voltage and current follower. The proposed CCII+ has 3-dB cutoff frequency of 10MHz for the range over bias control current $100{\mu}A$ to 10mA. The range of output current control is four decade. The power dissipation of the CCII+ is 4.5mW at supply voltage of ${\pm}2.5V$.