• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.140-142
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• 2003

Small impedances in the superconducting Parallel circuits cause unequal distribution of the currents in the circuits. This results in Quenches or losses in some superconducting parts. This paper presents the fabrication and test results of a multi-interphase transformers (IPT) for equal current distribution in parallel circuits. Test results show that the IPT can effectively make the current distribution uniform in parallel circuits that have unequal resistances.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1261-1267
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• 2007

Although LEDs have been used in various applications with improving the brightness and luminous efficacy, the electrical and optical characteristics of high power LED varies at different temperature and starting time. In this paper, optimal heat sink and apparatus design were conducted using IR camera and ICEPAK on the LED bulb consisting with fourteen LED array. The temperatures of heat sink and LED device of the designed LED bulb without cooling pan were $74^{\circ}C\;and\;96.8^{\circ}C$, respectively, showing in good themal characteristics. For high efficiency driving circuit of LED array adopted optimal heat sink design, driving circuits of constant voltage and current circuits were suggested and fabricated. As a result the efficacy of all driving circuits showed more than 20 lm/W. Also, the constant current circuits are suitable for signal lamp, hallway lamp, and flash lamp having short operating time(about 30 min). On the other hand, a reading light and indoor lamp having long operating time can be controlled by constant voltage circuit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.184-195
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• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.149-152
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• 2000

We propose simple analog MOS circuits producing the one-dimensional compact motion-sensing circuits. In the proposed circuit, the optical flow is computed by a number of local motion sensors which are based on biological motion detectors. Mimicking the structure of biological motion detectors made the circuit structure quite simple, compared with conventional velocity sensing circuits. Extensive simulation results by a simulation program of integrated circuit emphasis (SPICE) indicated that the proposed circuits could compute local velocities of a moving light spot and showed direction selectivity for the moving spot

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.9
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• pp.21-27
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• 1997

Square spiral inductors are designed with EM program in accordance with the inner diameter and the metal thickness which is 0.2.mu.m and 20.mu.m respectively. We propose a parameter extraction method based on the S-parameter. Lumped equivalent circuits of spiral inductors are analyed with reflection coefficient S$_{11}$, of witch freqency rnage is 1~10GHz. When metal thickness is 0.2.mu.m, S$_{11}$ with EM simulation is not the same as S$_{11}$ that of SPICE simulation. So we suggests a new lumped equivalent circuits which compensate circuits. Te new lumped equivalent circuits are adequate for other inductor with small scale at high frequencies.ncies.