• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.99-105
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• 2022

As the chip size gets smaller, the width of the electrode line is also fine, and the density of interconnections is increasing. As a result, RC delay is becoming a problem due to the difference in resistance between the capacitor layer and the electrical conductivity layer. To solve this problem, the development of electrodes with high electrical conductivity and dielectric materials with low dielectric constant is required. In this study, we developed low dielectric ink by mixing commercial PSR which protect PCB's circuits from external factors and PI with excellent thermal property and low-k characteristics. As a result, the ink mixture of PSR and PI 10:3 showed the best results, with a dielectric constant of about 2.6 and 2.37 at 20 GHz and 28 GHz, respectively, and dielectric dissipation was measured at about 0.022 and 0.016. In order to verify the applicability of future applications, various line-width transmission lines produced on Teflon were evaluated, and as a result, the loss of transmission lines using low dielectric ink mixed with PI was 0.12 dB less on average in S21 than when only PSR was used.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.5
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• pp.7-15
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• 2022

Since the direct and indirect damage caused by the fire in the underground utility tunnel will cause great damage to society as a whole, it is necessary to make efforts to prevent and control it in advance. The most of the fires that occur in cables are caused by short circuits, earth leakage, ignition due to over-current, overheating of conductor connections, and ignition due to sparks caused by breakdown of insulators. In order to find the cause of fire at an early stage due to the characteristics of the underground utility tunnel and to prevent disasters and safety accidents, we are constantly managing it with a detection system using image analysis and making efforts. Among them, a case of developing a fire detection system using CCTV-based deep learning image analysis technology has been reported. However, CCTV needs to be supplemented because there are blind spots. Therefore, we would like to develop a high-performance acoustic-based deep learning model that can prevent fire by detecting the spark sound before spark occurs. In this study, we propose a method that can collect sound in underground utility tunnel environments using microphone sensor through development and experiment of prototype module. After arranging an acoustic sensor in the underground utility tunnel with a lot of condensation, it verifies whether data can be collected in real time without malfunction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.169-174
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• 2023

Currently, overall power usage is also increasing as power demand such as homes, offices, and factories increases. The increase in power use also raised interest in standby power as a change in awareness of energy saving appeared. Home and office devices are consuming power even in standby conditions. Accordingly, there is a growing need to reduce standby power, and it aims to have standby power of 1W or less. An intelligent outlet uses a near-field wireless network to connect to a home network and cut or reduce standby power of a lamp or appliance connected to an outlet. This research aims to develop a monitoring system and an intelligent outlet that can remotely monitor the amount of electricity used in a lighting lamp or a home appliance connected to an outlet using a short-range wireless network (Zigbee). Also, The intelligent outlet and monitoring system developed makes it possible for a user to easily cut off standby power by using a portable device. Intelligent outlets will not only reduce standby power but also be applicable to fire prevention systems. Devices that cut off standby power include intelligent outlets and standby power cutoff switches, so they will prevent short circuits and fires.

• Journal of Life Science
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• v.33 no.5
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• pp.429-435
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• 2023

Epidemiological studies suggest that maternal infection, maternal stress, and environmental risk factors during pregnancy increase the risk of brain development abnormalities associated with cognitive impairment in the offspring and increase susceptibility to schizophrenia and autism spectrum disorder. Several animal models have demonstrated that maternal immune activation (MIA) is sufficient to induce abnormal brain development and behavioral defects in the fetus. When polyinosine:polycytodylic acid (poly I:C) or lipopolysaccharide (LPS), which is commonly used in maternal immune activation animal models, was introduced into a pregnant dam, an increase in pro-inflammatory cytokines and microglial activity was observed in the offspring's brain. Microglia are brain-resident immune cells that play a mediating role in the central nervous system, and they are responsible for various functions, such as phagocytosis, synapse formation and branching, and angiogenesis. Several studies have reported that microglia are activated in MIA offspring and influence offspring behavior through interactions with various cytokines. In addition, it has been reported that they play an important role in brain circuits through interactions with neurons and astrocytes. However, there is controversy concerning whether microglia are essential to brain development or lead to behavioral defects, and the exact mechanism remains unknown. Therefore, for the potential diagnosis and treatment of brain developmental disorders, a functional study of microglia should be conducted using MIA animal models.

• Journal of IKEEE
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• v.27 no.1
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• pp.45-52
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• 2023

Cold-junction correction(CJC) and disconnection detection circuit design of various thermocouples(TC) and multi-channel TC interface circuit using them were designed. The CJC and disconnection detection circuit consists of a CJC semiconductor device, an instrumentation amplifier(IA), two resistors and a diode for disconnection detection. Based on the basic circuit, a multi-channel interface circuit was also implemented. The CJC was implemented using compensation semiconductor and IA, and disconnection detection was detected by using two resistor and a diode so that IA input voltage became -0.42V. As a result of the experiment using R-type TC, the error of the designed circuit was reduced from 0.14mV to 3㎶ after CJC in the temperature range of 0℃ to 1400℃. In addition, it was confirmed that the output voltage of IA was saturated from 88mV to -14.2V when TC was disconnected from normal. The output voltage of the designed circuit was 0V to 10V in the temperature range of 0℃ to 1400℃. The results of the 4-channel interface experiment using R-type TC were almost identical to the CJC and disconnection detection results for each channel. The implemented multi-channel interface has a feature that can be applied equally to E, J, K, T, R, and S-type TCs by changing the terminals of CJC semiconductor devices and adjusting the IA gain.

• Journal of the Korean Geotechnical Society
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• v.24 no.2
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• pp.77-86
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• 2008

The disturbance zone and measured values are affected by the size of the penetrometer. The local value may be measured by the smaller penetrometer. An ultra small Micro-Cone penetrometer (5mm in outer diameter) is designed and manufactured to characterize soil properties with minimum disturbance during penetration tests. The tip resistance is measured by using stain gauges attached near the Micro-Cone. In addition, the friction sleeve is adopted to effectively remove the skin friction from the tip resistance. Design concern includes the installation of stain gauges, circuits, penetration systems, penetration rate, sampling rate, operating temperature, and calibration. Application tests show that the clay interface, and the soil layers consisting of clay and sand are clearly detected by the Micro-Cone. Furthermore, the cone tip resistances measured by the Micro-Cone and the miniature cone (16mm in outer diameter) are similar. Note the resolution is much higher in the Micro-Cone. This study shows that the Micro-Cone may effectively detect the soil interface with high resolution, and with minimum disturbance.

• Mood & Emotion
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• v.10 no.1
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• pp.13-21
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• 2012

Suicide is a complex behavior associated with various neurobiological and psychosocial factors. It is considered that genetic polymorphism combined with environmental stress such as child-adolescent trauma make differences in neurobiological systems, which cause psychiatric disorders or pessimistic personality, impulse-aggressive behaviors, lack of judgment, and finally result in suicidal behavior. Much progress in the neurobiology of suicide has been made over the several decades. There seems to be a hereditary disposition to suicide independent of psychiatric disorder. The changes in neurotransmitters, neurohormones, neurotrophic factors, cytokines, lipid metabolisms related with their genetic polymorphism can contribute to disturbance of signal transductions and neuronal circuits vulnerable to suicide. It is likely that the main factors are dysfunctions of serotonin (5-HT) and hypothalamus-pituitary-adrenal (HPA) axis. Our understanding about the neurobiology of suicide is still limited. However, clinical practice could be assisted by neurobiological findings capable of making the detection of risk populations with higher sensitivity and the development of new treatment interventions. The settlement of biological markers in suicidal behaviors and their relationships is required.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.