• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.10
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• pp.19-26
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• 1992

Generally, When we calculate notch angle to eliminate some selected harmonics using PWM inverter, we put the previously analysed notch angle formed by look-up table into memory, or perform the program to claculate notch angle iteratively with Fourier series. But, these methods are very difficult to control the system in real-time. Now, in this paper, we propose a new method to calculate notch angle using Walsh series, design real-time logic circuits which can be applied in 3 phase circuits and make one chip to reduce complexity and size of circuits using VLSI design technique.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.1
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.43-53
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• 1997

In this paper, the optimal synthesis algorithm of multiple-valued logic circuits using universal logic modules (ULM) U$_{f}$ based on 3-variable ternary reed-muller expansions is presented. We check the degree of each varable for the coefficients of reed-muller expansions and determine the order of optimal control input variables that minimize the number of ULM U$_{f}$ modules. The order of optimal control input variables is utilized the realization of multiple-valued logic circuits to be constructed by ULM U$_{f}$ modules based on reed-muller expansions using the circuit cost matrix. This algorithm is performed only unit time in order to search for the optimal control input variables. Also, this algorithm is able to be programmed by computer and the run time on programming is O(p$^{n}$ ).

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.1
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• pp.19-24
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• 2013

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.

• Molecules and Cells
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• v.41 no.5
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• pp.373-380
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• 2018

Synapses and neural circuits form with exquisite specificity during brain development to allow the precise and appropriate flow of neural information. Although this property of synapses and neural circuits has been extensively investigated for more than a century, molecular mechanisms underlying this property are only recently being unveiled. Recent studies highlight several classes of cell-surface proteins as organizing hubs in building structural and functional architectures of specific synapses and neural circuits. In the present minireview, we discuss recent findings on various synapse organizers that confer the distinct properties of specific synapse types and neural circuit architectures in mammalian brains, with a particular focus on the hippocampus and cerebellum.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.8
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• pp.517-524
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• 2004

In this paper, a novel zero-voltage-switching(ZVS) resonant DC-DC converter is proposed. It is composed of two symmetrical active-clamped circuits, the converter can be achieve ZVS in each switches. Also, active clamp capacitor ratios($\alpha$) of proposed circuit can be reduce a peak stress of switching voltage for each main switch. Simulation results using Pspice 9.2 ver and $C^{++}$ characteristic analysis show a provement for the validity of theoretical analysis. The analysis of the proposed Current-Fed Push Pull type DC-DC converter is generally described by using normalized parameter, and achieved an evaluated characteristic values which is needed to design a circuit. We confirm a rightfulness theoretical analysis by comparing a theoretical values and experimental values obtained from experiment using MOSFET as switching devices.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.3
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• pp.106-112
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• 2016

The high-voltage pulse generator consists of transformers of fundamental wave and harmonic waves, and shunt capacitors. The pulse has the fundamental wave and the harmonic waves that have been as a series circuit by the transformers to make high voltage pulse. This paper shows that pulse generator circuit is analyzed by using transformer equivalent circuits with the effect of load and simulated in time domain using Matlab program. The output voltage of pulse were obtained to 2.5kHz, 2.0kV. In high voltage circuit, capacitors are related to frequency band pass characteristics. Also, it is shown that the voltage of output pulse increases according to the growth of load.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.147-156
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• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

• Journal of Power Electronics
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• v.4 no.4
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• pp.197-204
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• 2004

Two-stage Power-Factor-Correction (PFC) converters are the most common circuits for drawing sinusoidal and in phase current waveforms from an ac source with a good regulated output voltage. The first stage is a boost PFC converter with average-current-mode control for achieving the near-unity power factor and the second stage is a forward converter with voltage-mode control to regulate the output voltage. Stability analysis and design methods of two-stage PFC converters have previously been discussed using linear models. Recently, new nonlinear phenomena have been detected in pre-regulator boost PFC circuits and a new nonlinear model has been proposed for pre-regulated PFC converters. Therefore, investigation of two-stage PFC converters from the nonlinear viewpoint becomes important because the second stage DC/DC converter adds more complexity to the circuit. So, this paper introduces a study of the stability of two-stage PFC converters. A novel nonlinear model of two-stage PFC converters is proposed. Then, a stability analysis is made based upon this nonlinear model. The high correspondence between the simulated and experimental results confirms our analysis.