• Journal of Electrical Engineering and Technology
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• v.4 no.3
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• pp.396-400
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• 2009

In this paper, electromagnetic topology (EMT) was used to analyze the electromagnetic compatibility (EMC) of RF circuits including passive and active components. It is difficult to obtain usable results for problems relating to electromagnetic coupling in complex systems when using conventional numerical or experimental methods. Thus it is necessary to find a new methodology for analyzing EMC problems in complicated electromagnetic environments. In order to consider the nonlinear characteristics of active components, a SPICE diode model was used. A power detector circuit and the receiver circuit of a radio control (RC) car were analyzed and experimented in order to verify the validity of this method.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.10
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• pp.501-507
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• 2001

In this paper, new high-efficiency zero voltage switching (ZVS) AC-DC boost converter is proposed to achieve power factor correction by simplifing energy recovery circuit. A lot of high power factor correction circuits have been proposed and applied to increase input power factor and efficiency. Most of these circuits may obtain unity power factor and achieve sinusoidal current waveform with zero voltage or/and zero current switching. However, it is difficult for them to obtain low cost, small size, low weight, and low noise. The topology proposed to improve these problems can compact the devices in circuit and can achieve high efficiency ZVS AC-DC boost converter. Simulation and experimental results show that this topology is capable of obtaining high power factor and increasing the efficiency of the system.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.2
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• pp.46-52
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• 2012

This paper proposes a novel single-phase ac-ac converter topology based on the Z-source concept. The converter provides buck-boost function and plays the role of frequency changer. Compared to the traditional ac-dc-ac converter, it uses fewer devices, realizes direct ac-ac power conversion, and has a simpler circuit structure, so as to have higher efficiency and better circuit characteristics. Compared to the traditional matrix converter, it provides a wider voltage regulation range. The circuit topology, operating principle, control method and simulation results are given in this paper, and the rationality and feasibility is verified.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.227-230
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• 2001

This paper deals with a bidirectional ac-dc converter used in ups system application. We propose a Voltage-Source-Charge-Pump-Power-Factor-Correction(VS-CPPFC) ac-dc converters. First of all, we propose a charge pump power-factor-correction converter. Secondly, we derive and analyse a unity power factor condition. The proposed topology is based on a half-bridge for the primary and a current-fed push pull for the secondary side of a high frequency isolation transformer. The advantage of bidirectional flow of power achieved by using the same power components is that the circuit is simple and efficient. And the galvanically isolated topology is specially attractive in battery charge/discharge circuits in ups system. We design equivalent model for the steady-state circuit and analyse operation waveforms for each mode. We show that the proposed model can be applied to ups system by simulation processes.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.7-8
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• 2015

In this paper a cell-to-cell fast charge balancing circuit for the Lithium-Ion battery module is proposed. In the proposed topology the energy in a high voltage cell is transferred directly to a low voltage cell through the operation of the dc-dc converter. Furthermore, the charge balancing can be performed regardless of the battery operation whether it is being charged, discharged or relaxed. The monitoring circuit composed of a DSP and a battery monitoring IC is designed to monitor the cell voltage and detect the inferior cell thereby protecting the battery module from failure. In order to demonstrate the performance of the proposed topology, a prototype circuit was designed and applied to 12 Lithium-Ion battery module. It has been verified with the experiments that the charge equalization time of the proposed method was shorter compared with those of other methods.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.3
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• pp.214-220
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• 2022

This paper proposes a test device designed for developing a high-voltage multilayer ceramic capacitor (MLCC). The proposed topology consists of an energy recovery circuit for charging/discharging capacitor, a flyback converter, and a boost converter for supplying power and a bias voltage application to the energy recovery circuit. The energy recovery circuit designed with a half-bridge converter has auxiliary switches operating before the main switches to prevent excessive current from flowing to the main switches. A prototype has been designed to verify the reliability of target capacitors following the voltage fluctuation with a frequency range below 65 kHz. To conduct high root mean square (RMS) current to the capacitor as a load, the MLCC test was conducted after the topology verification was completed through the film capacitor as a load. Through the agreement between the RMS current formula proposed in this paper and the MLCC test results, the possibility of its use was demonstrated for high-voltage MLCC development in the future.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.105-106
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• 2013

This paper proposes a new topology with active switched-capacitor and switched-inductor impedance network, which can obtain a high boost factor with small shoot-through time. The proposed topology uses an active switched capacitor and switched-inductor impedance network in order to couple the main circuit and input dc source for boosting the output voltage. The proposed topology contains all advantages of the classical Z-source inverter. Comparing with other topologies, the proposed topology uses lesser component and the voltage boost inversion ability significantly increases. The theoretical analysis, pulse width modulation control strategies, and a comparison with classical ZSI have been given in this paper. Both simulation and experimental results will be presented to verify the advantages of the proposed topology.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.646-647
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• 2007

The topology processor uses the status of circuit breakers as input. It operates on the bus section connectivity data, which is stored in the data base, to determine the bus/branch topology of the network. This output of the topology processor forms part of the input to the state estimation or dispatcher power flow. This paper describes the development of the topology processor using matrix structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.5
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• pp.297-306
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• 1986

This paper surveys circuit switching local area networks(LANs) whit topology of ring, mesh, bus and star. Emphasis of this study is given on the conceptual switching technologies of these LANs.