• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.1
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• pp.299-305
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• 2014

The purpose of this study was to determine the effect of a task-related circuit training in improving the function of lower extremity and quality of life in patient with hemiplegia. A total 25 paients with hemiplegia selected, the volunteers were randomly divided into a task-related circuit training group of 13 people and a treadmill training group of 12 people. The two groups received treadmill training for 30 minutes a day, 5 days a week for 8 weeks. The experimental group was additionally received the task related circuit training for 30 minutes. The assessment comprised of testing the patient's strength, walking, balance ability(strength of knee, balance ability, 10m walking test) and making use of the stroke impact scale. Post treatment, compared to the treadmill training group, task-related circuit training group showed significantly increased strength of knee extensor, flexor and balance ability, stoke impact scale(p<.05). The findings of this study suggest that a task-related circuit training can improve function of lower extremity and quality of life in patient of hemiplegia. Further studies with a greater sample size and a various intervention are needed to generalize the findings of the present study.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2989-2996
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• 1998

As the circuit density of VLSI grows and its performance improves, delay fault testing of VLSI becomes very important. Delay faults in a circuit can be categorized into two classes, gate delay faults and path delay faults. This paper proposed two methods in dynamic memory usage in the path delay fault simulation. The first method is similar to that used in concurrent fault simulation for stuck-at faults and the second method reduces dynamic memory usage by not inserting a fault descriptor into the fault list when its value is X. The second method, called Implicit-X method, showed superior performance in both dynamic memory usage and simulation time than the first method, called Concurrent-Simulation-Like method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.34-41
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• 2007

We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

• Journal of Power Electronics
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• v.17 no.2
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• pp.514-521
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• 2017

This paper proposes a shadowing compensation method for the solar modules of grid-connected photovoltaic generation systems. The shadowing compensator (SC) implemented by the proposed shadowing compensation method is used only for the solar modules that can be shaded by predictable sources of shading. The proposed SC can simplify both the power circuit and the control circuit as well as improve power efficiency and utilizes a voltage equalizer configured by a modified multi-winding fly-back converter. The proposed SC harvests energy from the entire solar cell array to compensate for the shaded sub-modules of the solar cell array, producing near-identical voltages of all shaded and un-shaded sub-modules in the solar cell array. This setup prevents the formation of multiple peaks in the P-V curve under shaded conditions. Hardware prototypes are developed for the SCs implemented by the conventional and modified multi-winding fly-back converters, and their performance is verified through testing. The experimental results show that both SCs can overcome the multiple peaks in the P-V curve. The proposed SC is superior to the SC implemented by the conventional multi-winding fly-back converter.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.6
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• pp.361-368
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• 2002

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.5
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• pp.334-339
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• 2012

A study on electrical and electronic equipment will occur in the atmosphere, which is essential to cut the power to prevent the waste of power by power measurement technology development and to develop the technology to do this operation is the main core of standby power to detect and block it and return the configured for software and hardware, while the actual construction to ensure stability through field testing and debugging of problems improved accordingly, as well as ease of installation and so it could be done while the test. In addition, in terms of basic hardware switching of standby power when blocking, reducing stress and ensure stable operation and circuit design, power off and back to ensure stable operation even when a protection circuit is applied.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.980-986
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• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.624-626
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• 2005

디지털 컴퓨터와 측정시스템의 발달로 대전력시험 데이터들은 시험자에 의한 분석이 아닌, 분석프로그램을 이용한 자동 분석이 가능해 졌다. 그러나 분석 프로그램을 이용하여 시험데이터를 분석해야 할 경우, 분석프로그램의 객관적인 신뢰성이 먼저 확보되어야 한다. 최근 들어 이러한 문제점을 보완하기 위하여, STL(Short-circuit Testing Liason)에서는 분석프로그램의 신뢰성평가를 위해 TDG(Test Data Generator)를 개발하였다. 이를 이용하면 대전력시험기관에서 사용하는 분석프로그램간의 객관적인 비교 및 평가가 가능하다. 따라서 본 논문에서는 STL에서 배포한 TDG를 이용하여, Crest, RMS, %DC 분석프로그램 알고리즘의 신뢰성을 평가해 보았다. 또한, STL에서 제시한 reference curve는 50[Hz]를 기본주파수로 하고 있기 때문에, 평가의 신뢰성을 높이기 위해 본 논문에서는 우리나라의 실정에 맞는 60[Hz]의 reference curve도 추가로 고려하였다. 신뢰성 평가 결과 모든 reference curve에 대한 분석알고리즘의 측정불화도가 STL에서 제시하는 범위에 존재함을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.29-38
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• 1999

This paper presents a new algorithm RICP(Redundancy Identification using Critical-pair Paths) to identify untestable faults in combinational logic circuits. In a combinational logic circuit, untestable faults occurred by redundancy of circuits. The redundancy of a circuit can be detected by analyzing areas of fanout stem and reconvergent gates. The untestable faults are identified by analyzing stem area using Critical-Pair path which is an extended concept of critical path. It is showed that RICP is better than FIRE(Fault Independent REdundancy identification) algorithm in efficiency. The performance of both algorithms was compared using ISCAS85 bench mark testing circuits.