• 제목/요약/키워드: Circuit testing

검색결과 418건 처리시간 0.033초

마이크로프로세서 제어를 이용한 DC-DC Buck Converter 설계 (Design of DC-DC Buck Converter Using Micro-processor Control)

  • 장인혁;한지훈;임홍우
    • 공학기술논문지
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    • 제5권4호
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    • pp.349-353
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    • 2012
  • Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

DC/DC 강압컨버터용 MOSFET의 TID 및 SEGR 실험 (TID and SEGR Testing on MOSFET of DC/DC Power Buck Converter)

  • 노영환
    • 한국항공우주학회지
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    • 제42권11호
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    • pp.981-987
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    • 2014
  • DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. DC/DC 컨버터는 MOSFET(산화물-반도체 전계 효과 트랜지스터), PWM-IC(펄스폭 변조 집적회로) 제어기, 인덕터, 콘덴서 등으로 구성되어있다. MOSFET는 스위치 기능을 수행하는데 코발트 60 ($^{60}Co$) 저준위 감마발생기를 이용한 TID 실험에서 방사선의 영향으로 문턱전압과 항복전압의 변화와 SEGR 실험에 적용된 5종류의 중이온 입자는 MOSFET의 게이트(gate)에 영향을 주어 게이트가 파괴된다. MOSFET의 TID 실험은 40 Krad 까지 수행하였으며, SEGR 실험은 제어보드를 구현한 후 LET(MeV/mg/$cm^2$)별 cross section($cm^2$)을 연구하는데 있다.

조합논리회로의 고장 검출율 개선을 위한 회로분할기법 (Circuit partitioning to enhance the fault coverage for combinational logic)

  • 노정호;김상진;이창희;윤태진;안광선
    • 전자공학회논문지C
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    • 제35C권4호
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    • pp.1-10
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    • 1998
  • Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

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차단기 특성 시험 시스템의 개발에 관한 연구 (A Study on the Development of Circuit Breaker Testing System)

  • 김동수;원호성;김철환
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.650_651
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    • 2009
  • 현재 한국전기연구원에서는 년간 약 1,000여대 이상의 차단기류에 대하여 사용전 검사 시험을 실시하고 있다. 차단기류의 사용전 검사 시험 항목은 개폐 특성에 대한 검증이 주를 이룬다. 현재 사용하고 있는 차단기 개폐특성 시험 설비는 약 20여년을 사용하여 보수가 필요한 시점에 도달하였다. 본 논문에서는 차단기류의 개폐특성 시험에 사용하던 차단기 특성 시험 시스템의 단점을 보완하여 시험의 신뢰성 및 사용자 편의성을 향상시킨 시험 시스템을 개발하고자 한다.

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압전소자 밸브 특성에 관한 실험적 연구 (Experimental Study on the Characteristics of Pneumatic Valve with Piezoelectric Element)

  • 윤소남;함영복;조정대;유찬수
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2003년도 춘계학술대회 논문집
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    • pp.828-831
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    • 2003
  • The benefits of the pneumatic valve with piezoelectric element are faster response times, low energy consumption, and the ability to be used in hazardous environments and field bus systems. In this paper, PZT actuator, 2 and 3 stages pneumatic valve were designed and manufactured. Also. characteristics of the pneumatic valve with piezoelectric element were tested with a testing system. It is confirmed that the PZT actuator is useful one for controlling the direction of pilot valve.

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A Study on Core Structure of High Frequency Transformer to Improve Efficiency of Module-Integrated Converter

  • Yoo, Jin-Hyung;Jung, Tae-Uk
    • Journal of Magnetics
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    • 제19권3호
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    • pp.295-299
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    • 2014
  • Recently, module-integrated converter (MIC) research has shown interest in small-scale photovoltaic (PV) generation. The converter is capable of efficient power generation. In this system, the high frequency transformer should be made compact, and demonstrate high efficiency characteristics. This paper presents a core structure optimization procedure to improve the efficiency of a high frequency transformer of compact size. The converter circuit is considered in the finite element analysis (FEA) model, in order to obtain an accurate FEA result. The results are verified by the testing of prototypes.

대전류표준측정시스템을 위한 STL의 활동 (The activities of Short-circuit Testing Liaison for the high-current standard measurement system)

  • 신영준;김익수;김민규
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 하계학술대회 논문집 A
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    • pp.437-439
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    • 2001
  • The plan of intercomparison test for high-current system was discussed concretely in the technical committee of STL in 2000. This paper describes the present state of the world, the plan & procedure of intercomparison test and test expenses for high-current system. In conclusion, this mentioned the matters that our country should prepare urgently.

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IEEE 1149.1 구조에서 다중 동적 신호 검출 (Detecting the Multiful Dynamic Signals on IEEE 1149.1 Structure)

  • 김상진;오주환
    • 한국산업정보학회:학술대회논문집
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    • 한국산업정보학회 2001년도 춘계학술대회논문집:21세기 신지식정보의 창출
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    • pp.209-216
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    • 2001
  • A key advantage of boundary scan technology is the ability to observe data at device inputs and control data at device outputs, independent of on-chip system logic. But, this method has a disadvantage for detecting of faults that changes their states very fast. We present a method to solve this problem and make it possible to detect the signals. We shown the simulation results of testing a circuit that has fast signal above the clock speed.

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Efficient Path Delay Test Generation for Custom Designs

  • Kang, Sung-Ho;Underwood, Bill;Law, Wai-On;Konuk, Haluk
    • ETRI Journal
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    • 제23권3호
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    • pp.138-149
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    • 2001
  • Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

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정전기 방전시의 소나무목분의 최소착화에너지 측정에 관한 연구 (A Study of Measurement of Minimum Ignition Energy for Pine Tree Dust on Electrostatic Discharges)

  • 이동훈;박한석
    • 한국안전학회지
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    • 제13권3호
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    • pp.74-79
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    • 1998
  • To establish measuring method for minimum ignition energy of explosive powders caused by electrostatic discharge, A measuring method(Hartman) using a very small quantity of pine tree testing powder was proposed, and the influence of discharge current limiting resistance connected in series into a capacitive discharge circuit on ignition energies of explosive powders was investigated. As a result the minimum ignition energy was 42.25mJ when discharge current limiting resistance 300 $k\Omega$.

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