• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 합동춘계학술대회 논문집 전기물성,응용부문
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• pp.133-134
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• 2008

This paper describes a testing method to assess the reliability of the epoxy bushing used for the vacuum circuit breaker(VCB). Especially, in order to show the long-term durability of epoxy bushing in a short testing duration, the extremely accelerated electric stress applying test plan was adopted.

• 전자공학회논문지C
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• 제35C권8호
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

• 한국통신학회논문지
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• 제29권10A호
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• pp.1205-1214
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• 2004

CMOS 회로에서 발생하는 물리적인 결함에 대해서 전류 테스팅은 전압 테스팅으로 검출할 수 없는 많은 결함을 효율적으로 검출할 수 있는 기법이다. 테스트 회로에 존재하는 결함이나 장애의 영향을 기술하기 위해서 사용되는 고장모델은 실제적인 장애를 정확하게 모델링해야 한다. 본 논문에서는 전류 테스팅에 자주 이용되는 고장모델을 위한 효율적인 중첩 알고리즘을 제안한다. ISCAS 벤치마크 회로의 모의실험을 통하여 제안된 방식이 고려되는 고장의 수를 효과적으로 감소시킬 수 있고 다양한 전류 테스팅 방식의 고장모델에 더 적합함을 확인하였다.

• 전자공학회논문지A
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• 제32A권12호
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1409-1412
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• 1994

The electrodes for Phosphoric Acid Fuel Ceil were fabricated as a condition of PTFE contents in electrocatalyst layer and sintering temperature in the range of 25 -- 65 wt% and 310 -- $390^{\circ}C$, respectively. For the fabricated electrode, the accelation testing of cathode half cell at open circuit potential was investigated. While the performance of electrode showed maximum at the low level of PTFE contents in the initial stage of accelation testing, the maximum performance was shifted to higher PTFE contents of 45wt% after 24hrs accelation testing.

• Journal of Magnetics
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• 제22권1호
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• pp.122-132
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• 2017

This study dealt with the design process of the 78 kW permanent magnet synchronous generator for engines. After the calculation of the basic dimensions through a theoretical method in the process of initial model design, FEA (finite-element analysis) and a d,q-axis equivalent circuit were used to identify the generator characteristics depending on the number of poles. With the use of the space harmonic analysis method, the back-EMF (electromotive force) and THD were checked, and then the number of slots was determined. In addition, the most optimized generator dimensions were determined through a sizing optimization technique. Based on this, the optimum model with enhanced efficiency, material costs, and temperature characteristics was derived, and the availability of the design method was confirmed through a comparative analysis of the initial and optimum models.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.2033-2044
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• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2485-2492
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• 2018

The rapid development of large-scale integrated circuits has brought great challenges to the circuit testing and diagnosis, and due to the lack of exact fault models, inaccurate analog components tolerance, and some nonlinear factors, the analog circuit fault diagnosis is still regarded as an extremely difficult problem. To cope with the problem that it's difficult to extract fault features effectively from masses of original data of the nonlinear continuous analog circuit output signal, a novel approach of feature extraction and dimension reduction for analog circuit fault diagnosis based on wavelet packet decomposition, local linear embedding algorithm, and clone selection algorithm (WPD-LLE-CSA) is proposed. The proposed method can identify faulty components in complicated analog circuits with a high accuracy above 99%. Compared with the existing feature extraction methods, the proposed method can significantly reduce the quantity of features with less time spent under the premise of maintaining a high level of diagnosing rate, and also the ratio of dimensionality reduction was discussed. Several groups of experiments are conducted to demonstrate the efficiency of the proposed method.

• 한국전기전자재료학회논문지
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• 제16권4호
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• pp.351-357
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• 2003

An easy learning elevator originated is opened to compare the existed teaming equipment, and it had a high studied efficiency that the sequence control circuit can open and close with the wire. The structure of equipment to be controlled from the first floor to the fifth floors is demostrated by the constructive apparatus with the lamps to express the function of the open-close of the door according to the cage moving with a mechanical actuation of the forward reverse breaker and the motor of load, and the mechanical actuation of hand-operation control components of push-button S/W and L/S and relay etc. These components let connect each other in order to control of the elevator function with the auto program and the designed sequence control circuit. Consequently the cage could go and come till 1∼5 steps with an auto program of the elevator and the sequence control circuit. The sequence control circuit is controlled by the step of forward and reverse to follow as that the sensor function of L/S1 ∼ L/S5 let posit with the control switchs of S/W1 ∼ S/W5 of PLC testing panel and switchs of S/W1 ∼ S/W5 installed on the transparent acryl plate of the frame. In here, improved apparatus is the hand-auto operation combined learning equipment to study the principle and technique of the originate sequence control circuit and the auto program of PLC.