• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2002년도 춘계학술대회논문집
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• pp.147-152
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• 2002

This paper was studied on corrosion of heat exchanger tube for absorption refrigeration machine. In the 62 % lithium bromide solution at $60^{\circ}C$, polarization test of Cu, Al-brass, 10 % cupro nickel(90-10 % Cu-Ni) and 30 % cupronickel(70-30 % Cu-Ni) tube was carried out. And polarization behavior, polarization resistance characteristics, open circuit potential, anodic polarization of heat exchanger tube for absorption refrigeration machine were considered. The main results are as following: The open circuit potential of Al-brass tube becomes less noble than that of Cu tube, corrosion current density of that becomes lower than Cu tube. The open circuit potential of cupronickel tube is more noble than that of Cu tube, corrosion current density of that is controlled than Cu tube. The passivation critical current of 30 % Cu-Ni tube is lower than that of 10 % Cu-Ni tube, potential of passive region of that is more wide than 10 % Cu-Ni tube.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1999년도 제14차 학술회의논문집
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• pp.281-283
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• 1999

This topic presents an inductor short turn testing. From the rudimentary principles, the quality factor(Q) decreases due to inductor short turn. Frequency response varies because of the variation of circuit inductance and resistance. In general, short turn circuit testing is performed by comparing the ratio of an inductance and resistance of inductor in that particular circuit. An alternative method can be done by considering the response of second order circuit which can give both dynamic and static testing, whereas static testing give an error results not more than 2 turns. For dynamic testing, the result is more accurate, which can test fur the short turn number form 1 turn onward.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• 대한전자공학회논문지
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• 제11권1호
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• pp.15-22
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• 1974

본 논문은 전류제어형각성저항 회로를 사용한 새로운 삼치전가산기의 구성에 관하여 논한다. 부성저항특성을 이용하여 먼저 특수한 반가산기를 설계하고 이에 의하여 전가산기를 구성한다. 이평가계기는 부성저항 회로와 쇼트키-베리어 다이오드를 사용한 삼자정 회로에 의해 구성되며, 두 입력신호가 모두 "2"일 경우 Sum과 Carry 출력이 각각 "0"과 "1"의 간을 갖는다. 여기에 제안한 전가산기는 종래의 전가산기에 비하여 게이트 수가 감소되고, 속도가 개선된다. 회로소자는 트랜지스터와 쇼트키-베리어 다이오드, 저항만을 사용하여 IC화하는데 편리하게 하였다.

• 대한전기학회논문지:전력기술부문A
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• 제50권1호
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• pp.38-44
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• 2001

For double-circuit transmission line systems, an accurate digital distance relaying algorithm immune to the reactance effect is proposed. The apparent impedance calculated by the distance relay is influenced by the combined reactance effect of the fault resistance and the load current as well as the mutual coupling effect caused by the zero-sequence current of the adjacent parallel circuit. To compensate the magnitude and phase of the estimated impedance, this algorithm uses phase angle difference between the zero(positive) sequence of the both side of the system seperated by the fault point. The impedance measuring algorithm presented used a current distribution factor to compensate mutual coupling effect instead of the collected zero-sequence current of the adjacent parallel circuit.

• 전자공학회논문지
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• 제52권10호
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• pp.33-46
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• 2015

본 논문에서는 ITRS(International Technology Roadmap for Semiconductors)를 따라 스케일 다운된 FinFET 소자의 디지털 및 아날로그 회로의 성능을 예측했다. 회로 성능의 정확한 예측을 위해 기생 커패시턴스와 기생 저항 모델을 개발해 3D Technology CAD 해석 결과와 비교해 오차를 2 % 미만으로 달성했다. 기생 커패시턴스 모델은 conformal mapping 방식을 기반으로 모델링 되었으며, 기생 저항 모델은 BSIM-CMG에 내장된 기생 저항 모델을 핀 확장 영역 구조 변수($L_{ext}$) 변화에 따른 기생 저항 성분 변화를 반영 할 수 있도록 개선했다. 또한, 공정 단위 변화에 대해 소자의 전압전류의 DC 특성을 반영하기 위해 BSIM-CMG 모델의 DC 피팅을 진행하는 알고리즘을 개발했다. BSIM-CMG에 내장된 기생 모델을 본 연구에서 개발한 저항과 커패시턴스 모델로 대체해 압축 모델 내부에 구현하여, SPICE 시뮬레이션을 통해 스케일 다운된 FinFET 소자의 $f_T$, $f_{MAX}$, 그리고 링 오실레이터와 공통 소스 증폭기의 기생 성분으로 인한 특성변화를 분석했다. 정확한 기생 성분 모델을 적용해 5 nm FinFET 소자까지 회로 특성을 정량적으로 제시했다. 공정 단위가 감소함에 따라 소자의 DC 특성이 개선될 뿐만 아니라 기생 성분의 영향이 감소하여, 회로 특성이 향상됨을 예측했다.

• 전자공학회논문지
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• 제54권5호
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• pp.11-16
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• 2017

RF MOSFET에서 관찰된 입력 저항의 주파수 종속 특성이 단순화된 입력 등가회로로부터 유도된 pole과 zero 주파수 수식을 사용하여 자세히 분석되었다. 이러한 이론적 분석을 사용하여 저주파에서 입력저항의 감소현상이 포화영역에서 소스와 pinch-off 영역 사이의 채널저항으로부터 발생되는 것을 발견하였다. 이와 같이 저주파에서 입력저항이 감소하는 채널 저항 효과는 채널저항을 변화시키면서 소신호 등가회로 모델링을 수행하여 물리적으로 입증되었다.

• 한국위성정보통신학회논문지
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• 제1권1호
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• pp.54-58
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• 2006

동작주파수를 쉽게 조절할 수 있는 신호생성용 안테나 (Antenna-Integrated Oscillator) 설계방법을 소개한다. 제안하는 회로는 광대역에서 부성저항을 갖는 능동회로 (Negative-Resistance Circuit)와 패치안테나로 구분되며, 오실레이터의 동작주파수는 안테나의 공진 주파수로 결정된다. 이러한 디자인 방법은 안테나와 오실레이터의 동작주파수 불일치로 인한 출력파워의 감소 가능성을 줄일 수 있다. 또, 제안하는 설계방법에서 안테나의 Feed 지점과 Feed 라인의 길이를 조절하여 최적의 출력파워를 낼 수 있음을 Load-Pull 시뮬레이션으로 확인하였다. C-band, X-band 회로를 각각 제작, 측정하였고 이를 통하여 설계방법의 타당성을 증명하였다.

• 대한전기학회논문지
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• 제33권11호
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• pp.456-463
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• 1984

The fast-rising high-voltage pulse generation circuit system of a theta pinch is both theoretically and experimentally investigated. The idealized model of this circuit system is a hybrid circuit system composed of three parts: a lumped circuit part being consisted of a capacitor bank and a spark switch connected in series, another lumped circuit part being consisted of the Blumlein transmission line, whose end load is the pinch coil. the voltage difference between two ends of the pinch coil is formulated by analyzing this hybrid circuit system by means of the law of the signal propagation in the transmission line and Kirchhoff's laws. The expedient numerical method for computer calculation is developed to generate the pulse profile of the voltage difference across the pinch coil. The period of the experimentally measured main pulse is a fourth of the theoretical one neglecting the resistance of the pinch coil. We attribute this discrepancy to the modelling in the theoretical calculation that hte resistance and inductance of the spark switch and capacitor bank are assumed to be constant through discharge. Therefore, we can see that the rise time of the imploding magnetic-field pulse is mainly dependent on the spark switch and capacitor bank.

• Nuclear Engineering and Technology
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• 제56권6호
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• pp.2395-2403
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• 2024

With the rapid development of DC high voltage accelerator, higher requirements have been raised for the design of DC high voltage power supply, requiring more stable high voltage with lower output ripple. Therefore, it also puts forward higher requirements for the parameter design of the voltage doubling rectifier circuit, which is the core component of the DC high voltage power supply. In order to obtain output voltage with better performance, the effects of the working frequency, the stage capacitance and the load resistance on the output voltage of the voltage doubling rectifier circuit are studied in detail by simulation. It can be concluded that the higher the working frequency of the transformer, the larger the stage capacitance, the larger the load resistance and the better the output voltage performance in a certain range. Based on this, a 2.5 MV voltage doubling rectifier circuit driven by a 120 kHz frequency transformer is designed, developed and tested for the power supply of the neutron source device towards BNCT. Experimental results show that this voltage doubling rectifier circuit can satisfy the design requirements, laying a certain foundation for the engineering design of DC high voltage power supply of neutron source device.