• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.4
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• pp.351-358
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• 2003

This paper describes distribution characteristics of switching surge voltage in stator windings of induction motor driven by IGBT PWM inverter. To analyze the voltage distribution between the turns and coils of stator winding, equivalent circuit model of induction motor including cable was proposed and high frequency parameter is computed by using finite-element method (FEM). From the electro-magnetic transient program (EMTP) simulation of the whole system for induction motor, feeder cable, and PWM inverter, the variable effect on rising time of the inverter, cable length, and switching frequency on the voltage distribution is also presented. In order to experiment, an induction motor, 380[V], 50[HP], with taps from one phase are built to consider the voltage distribution so that these results can be helpful when filter was designed to remove high dv/dt.

• Journal of the Semiconductor & Display Technology
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• v.4 no.1 s.10
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• pp.9-16
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• 2005

In this paper, with loosely coupled transformer Relies-parallel resonant type DC/DC converter is analyzed and adopted to the power source of a TFLM(Transverse Flux Linear Motor). To get more efficient operating mode of the series-parallel resonant type DC/DC converter, theoretical analysis using normalized parameters are accepted. The analysis includes a specially made ferrite transformer with two separately wound half cores in order to evaluate analytically and experimentally the changes in magnetizing the leakage fluxes and inductances caused by the distance between the halves. The proposed converter must be operated in switching Pattern III among the three switching patterns for the Zero Voltage Switching operation. According to Pulse Frequency Modulation(PFM) control method, the output voltage of the proposed circuit can be controlled. The results of the theoretical development are compared with practical measurements from a prototype system.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.3B no.1
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• pp.10-15
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• 2003

This paper presents the digital computer performance evaluations of the three-phase self-excited induction generator (SEIG) driven by the variable speed prime mover such as the wind turbine using the nodal admittance approach steady-state frequency domain analysis with the experimental results. The three-phase SEIG setup is implemented for small-scale rural renewable energy utilizations. The experimental performance results give a good agreement with those ones obtained from the digital computer simulation. Furthermore, a feedback closed-loop voltage regulation of the three-phase SEIG as a power conditioner which is driven by a variable speed prime mover employing the static VAR compensator (SVC) circuit composed of the thyristor phase controlled reactor (TCR) and the thyristor switched capacitor(TSC) is designed and considered herein for the wind-turbine driven the power conditioner. To validate the effectiveness of the SVC-based voltage regulator of the terminal voltage of the three-phase SEIG, an inductive load parameter disturbances in stand-alone are applied and characterized in this paper. In the stand-alone power utilization system, the terminal voltage response and thyristor triggering angle response of the TCR are plotted graphically. The simulation and the experimental results prove the effectiveness and validity of the proposed SVC which is controlled by the Pl controller in terms of fast response and high performances of the three-phase SEIG driven directly by the rural renewable energy utilization like a variable-speed prime mover.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.134-138
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• 2005

In this paper, we have developed a new type of the microwave phase conjugator for the active retrodirective antenna array. The circuit topology is consisted of a 2-port structure to avoid the complexity of LO and RF signal combination and matching, using the cascade connection of two single-ended mixers. The operating frequencies are 4.0 GHz, 2.01 GHz and 1.99 GHz for LO, RF, and IF, respectively. Conversion loss is measured to be -7 dB and 1-dB compression point 15 dBm with the LO power of 9 dBm. For the most important parameter, the isolation between RE leakage and IF signal is as high as 25 dB.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.29 no.5 s.236
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• pp.633-642
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• 2005

Nucleate pool boiling experiments for R11 under a constant wall temperature condition were carried out. A microscale heater array was used for the heating and the measurement of high temporal and spatial resolution by the Wheatstone bridge circuit. Very sensitive heat flow rate data were obtained by the control for the surface condition with high time resolution. The measured heat flow rate shows a discernable peak at the initial growth stage and reaches an almost constant value. In the thermal growth region, bubble shows a growth proportional to $t^{\frac{1}{5}}$. The bubble growth behavior is analyzed with a dimensionless parameter to compare with the previous results in the same scale. As the wall superheat increases, the departure diameter and the departure time increase, and the waiting time decreases. But the asymptotic growth rate is not affected by the wall superheat change. The effect of the wall superheat is resolved into the suggested growth equation. Dimensionless parameters of time and bubble radius characterize the thermal growth behavior well, irrespective of wall condition. The comparison between the result of this study and the previous results shows a good agreement at the thermal growth region. The quantitative analysis for the heat transfer mechanism is conducted with the measured heat flow rate behavior and the bubble growth behavior. The required heat flow rate for the volume change of the observed bubble is about twice as much as the instantaneous heat flow rate supplied from the wall.

• The Journal of the Acoustical Society of Korea
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• v.15 no.5
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• pp.82-89
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• 1996

Application fields of ultrasonic transducers can be divided into two categories, a high ultrasonic resolution required field and a high ultrasonic power required field. This paper is aimed to determine the optimal properties of the matching layers of the transducer for each of the applications. Further, it is aimed to optimize the properties of the matching layers that show satisfactory performances for both of the application fields. Through the direct time domain analysis of the transmission and reflection behavior of the ultrasonic wave, apart from the conventional equivalent circuit analysis, and Fourier transformation of its results, we found the optimum acoustic impedances of the matching layers. The newly determined layers provide much better transducer performance-57% at most-than those obtained with conventional design methods. Based on the results, we also found the optimal acoustic impedances of the layers good for both of the application fields. For te optimization, we developed a new transducer performance evaluation parameter that can be applied to any type of ultrasonic transducers.

• Journal of IKEEE
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• v.17 no.3
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• pp.260-266
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• 2013

The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.1-8
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• 2005

In this paper, design and implement 60W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of Doherty power amplifier is distinguishable; however implementation of assistance amplifer is difficult, though. To solve the problem, therefore, GCHD (Gate Control Hybrid Doherty) power amplifier is embodied to gate bias adjusament circuit of assistance amplifier to General Doherty power amplifier. Experiment result shows that $2.11\~2.17GHz$, 3GPP operating frequency band, with 62.55 dB gain, PEP output is 50,76 dBm, W-CDMA average power is 47.81 dBm, and -40.05 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than general power amplifier.