• Title/Summary/Keyword: Circuit Parameter

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Implementation of Impedance Matching Circuit for ATE (고속 ATE 시스템을 위한 임피던스 정합회로 구현)

  • Kim, Jong-Won;Seo, Yong-Bae;Lee, Yong-Sung
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.4 s.17
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    • pp.17-22
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    • 2006
  • In the manufacturing processes of semiconductor, test process is important for quality of products. In the manufacturing process of dynamic memory, memory test is more important. So, automatic test equipment(ATE) is used necessarily. But, according to increase of speed of dynamic memory operation, the rapid test equipment is needed. Impedance matching between ATE and dynamic memory is expected to be an important problem for making a rapid test equipment over 1Gbps. According to increase of speed, inner impedance of ATE also works on important parameter for test. This paper is about the method that is for impedance matching of inner impedance and coaxial cable occurring in manufacturing of ATE. We proved effects of inner impedance by electric theory and verified the method of impedance matching using computer simulation.

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Reactive Ion Etching Process Integration on Monocrystalline Silicon Solar Cell for Industrial Production

  • Yoo, Chang Youn;Meemongkolkiat, Vichai;Hong, Keunkee;Kim, Jisun;Lee, Eunjoo;Kim, Dong Seop
    • Current Photovoltaic Research
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    • v.5 no.4
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    • pp.105-108
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    • 2017
  • The reactive ion etching (RIE) technology which enables nano-texturatization of surface is applied on monocrystalline silicon solar cell. The additional RIE process on alkalized textured surface further improves the blue response and short circuit current. Such parameter is characterized by surface reflectance and quantum efficiency measurement. By varying the RIE process time and matching the subsequent processes, the absolute efficiency gain of 0.13% is achieved. However, the result indicates potential efficiency gain could be higher due to process integration. The critical etch process time is discussed which minimizes both front surface reflectance and etching damage, considering the challenges of required system throughput in industry.

Stability Improvement of 60 GHz Narrowband Amplifier Using Microstrip Coupled Lines

  • Chang, Woo-Jin;Lim, Jong-Won;Ahn, Ho-Kyun;Ji, Hong-Gu;Kim, Hae-Choen
    • ETRI Journal
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    • v.31 no.6
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    • pp.741-748
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    • 2009
  • We present an analysis of microstrip coupled lines (MCLs) used to improve the stability of a 60 GHz narrowband amplifier. The circuit has a 4-stage structure implementing MCLs instead of metal-insulator-metal (MIM) capacitors for the unconditional stability of the amplifier and yield enhancement. The stability parameter, U, is used to compare the stability of MCLs with that of MIM capacitors. Experimental results show that MCLs are more stable than MIM capacitors with the same capacitances as MCLs because the parasitic parallel resistances of MCLs are lower than those of MIM capacitors. Moreover, the bandwidth of an amplifier using MCLs is narrower than one using MIM capacitors because the parasitic series inductances of MCLs are higher than those of MIM capacitors.

Analytic Derivation of Single Transmission Line Parameters for Weakly Coupled Meander Line (약 결합된 Meander Line의 단일전송선 Parameter의 해석적 계산)

  • 염경환;강명숙
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.738-747
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    • 2000
  • In this paper it is shown that the meander line at the low frequency can be thought as the single transmission line whose characteristic impedance is approximately equal to that without coupling. But the length is contracted from that without coupling. The approximate contraction ratio is derived for weak coupling and is compared with the circuit simulation results and the EM simulation results. The formula are in good agreement with the simulation results in weak coupling.

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Flexible Partitioning of CDFGs for Compact Asynchronous Controllers

  • Sretasereekul, Nattha;Okuyama, Yuichi;Saito, Hiroshi;Imai, Masashi;Kuroda, Kenichi;Nanya, Takashi
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1724-1727
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    • 2002
  • Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

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Characteristic Analysis and Test of a Voice-Coil-Type LOA for Determination of Control Parameters (보이스코일형 LOA의 제어정수 산정을 위한 특성 해석 및 시험)

  • Jang, S.M.;Jeong, S.S.;Park, H.C.;Moon, S.J.;Park, C.I.;Chung, T.Y.
    • Proceedings of the KIEE Conference
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    • 1998.07a
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    • pp.278-280
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    • 1998
  • A voice-coil-type LOA consists of the NdFeB permanent magnets with high specific energy as the stator, a coil-wrapped nonmagnetic hollow rectangular structure, and an iron core as a pathway for magnetic flux. When applying a voice-coil-type LOA to the control system, we have to obtain the control parameters and circuit parameters, such as mass, coil inductance, coil resistance, thrust voltage & stroke, frequency & stroke and so on. Therefore, these parameter were determined from the analytical and experimental method.

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On Setting Method of the operating Parameters of SFCL in Transmission Systems Considering Power Protection Relay (계통보호릴레이와의 협조를 고려한 SFCL의 동작파라메타 설정방법에 대한고찰)

  • Hong, Won-Pyo
    • Proceedings of the KIEE Conference
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    • 1998.07c
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    • pp.1231-1234
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    • 1998
  • Design & Operation of power system for meeting increase of electric power demand is becoming more difficult and complex. One of reasons is increase of fault current. As one of the most effective methods for suppressing the fault current, installation of SFCL is expected. This paper describes a method of fault analyses of power system with SFCLs, and also discusses determination of specification of SFCLs, effects of limiting the fault current due to SFCLs by use of the model system of two - bus electric power system with parallel circuit model transmission line. Also, describes the definition of six specific parameters of SFCL for power system application & a proposal of design method of specific parameter of a resistance type SFCL in overhead transmission lines considering operation of protective relays.

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A Study on Voltage-Current characteristics of High-Voltage.Current Pulsed Discharge (고전압.대전류 pulse방전의 전압.전류특성에 관한 연구)

  • Seo, Kil-Soo;Cho, Kuk-Hee;Kim, Young-Bae;Lee, Hyeong-Ho
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1981-1983
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    • 2000
  • In this paper, the arc resistance of INPIStron is presented. It is need to the design of Pulsed power system and simulation on the circuit of pulsed power system with INPIStron switch. It is also possible to use this parameter to the part of discharge characteristics of Xenon lamp and the device with electrical discharge.

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AC Boss of multi-layer HTS Power transmission cable considering the current distribution by cable length variation (케이블 길이에 따른 층별 전류분류를 고려한 다층 고온초전도 송전케이블의 교류손실계산)

  • Lee, J.K.;Lee, S.W.;Cha, G.S.
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.810-812
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    • 2000
  • Superconducting transmission cable is one of interesting part in power application using high temperature superconducting wire as transformer. One important parameter in HTS cable design is transport current distribution because it is related with current transmission capacity and loss. In this paper, we calculate inductance and current distribution for 4-layer cable using the electric circuit model and compare calculation results of transport current losses by monoblock model and Norris equation

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Equivalent Circuit Parameter Extraction of four-port Microstrip Interconnects using Optimization (4포트 마이크로스트립 인터커렉트 회로 파라미터 추출에 대한 연구)

  • Shim, Min-Kyu;HwangBo, Hoon;Kim, Jong-Min;Nah, Wan-Soo;Seol, Byung-Soo;Lee, Jong-Sung;Lee, Hyung-Suk
    • Proceedings of the KIEE Conference
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    • 2006.10a
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    • pp.139-140
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    • 2006
  • 본 논문에서는 4포트 마이크로스트립 인터커넥트에 대한 새로운 등가모델을 제시하였다. 제시된 방법에서는 마이크로스트립 인터커넥트 중 선로의 방향이 변하는 부분에서 등가회로 파라미터인 커페시터 성분을 모델화하여 최적화 과정을 통해 값을 추출하였고, 시뮬레이션 결과와 측정치를 비교함으로써 등가회로모델의 유효성을 확인하였다.

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