• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1164-1171
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• 2014

Bulk Current Injection(BCI) test is a method of injecting current into Integrated Circuit(IC) using a current injection probe to qualify the standards of Electromagnetic Compatibility(EMC). This paper, we propose a microstrip coupler structure that can replace the BCI current injection probe that is used to inject a RF noise in standard IEC 62132-part 3 documented by International Electrotechnical Commission. Conventional high cost BCI probe has mostly been used in testing automotive ICs that use high supply voltage. We propose a compact microstrip coupler which is suitable for immunity testing of low power ICs. We tested its validity to replace the BCI injection probe from 100 MHz to 1,000 MHz. We compared the power[dBm] that is needed to generate the same level of noise between current injection probe and microstrip coupler by sweeping the frequency. Results show that microstrip coupler can inject the same level of noise into ICs for immunity test with less power.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.1
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• pp.71-81
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• 1987

To fuly utilize the availability of the ISDN, it is very important to develop the ISDN user terminals which can provide various user services. In this paper, the basic concept of the ISDN user terminal is briefly studied and, based on this study, a stimulus type digital telephone which can be connected directly to the ISDN is designed. This digital telephone can provide the basic voice service and has general functions such as voice encoding / decoding(PCM is used), user-network signalling, digital tone supply, channel selection, key pad and atatus display. Echo cancellation method is adopted for the digital subscirber loop transmission and user-network signalling is implemented according to the LAPD(Link Access Procedure on D-channel) protocol recommended by the CCITT's recommendations I.440-I.441. The validity of designed S/W and H/W functions are verified by testing them with ISDN circuit switching emulator described in the first part of this paper.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.480-480
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• 2000

In this paper, we proposed a fuzzy-neuro controller to control the speed of wound rotor induction motor with slip energy recovery. The speed is limited at some range of sub-synchronous speed of the rotating magnetic field. Control speed by adjusting resistance value in the rotor circuit that occurs the efficiency of power are reduced, because of the slip energy is lost when it passes through the rotor resistance. The control system is designed to maintain efficiency of motor. Recently, the emergence of artificial neural networks has made it conductive to integrate fuzzy controllers and neural models for the development of fuzzy control systems, Fuzzy-neuro controller has been designed by integrating two neural network models with a basic fuzzy logic controller. Using the back propagation algorithm, the first neural network is trained as a plant emulator and the second neural network is used as a compensator for the basic fuzzy controller to improve its performance on-line. The function of the neural network plant emulator is to provide the correct error signal at the output of the neural fuzzy compensator without the need for any mathematical modeling of the plant. The difficulty of fine-tuning the scale factors and formulating the correct control rules in a basic fuzzy controller may be reduced using the proposed scheme. The scheme is applied to the control speed of a wound rotor induction motor process. The control system is designed to maintain efficiency of motor and compensate power factor of system. That is: the proposed controller gives the controlled system by keeping the speed constant and the good transient response without overshoot can be obtained.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2149-2150
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• 2006

FLL 회로는 측정된 신호를 voltage to current converter를 거쳐 feedbak coil에 인가함으로써 외부 자장을 상쇄하여 SQUID의 동작점을 원점으로 회귀시켜 선형 구간을 유지하도록 하는 역할을 한다. FLL회로의 동자 범위와 특성을 분석하기 위해서는 일반적인 time-delayed feedback 회로와 사용된 OP amp의 slew rate, filter 의 amplitude 및 위상 특성, SQUID의 critical current, pickup coil 및 SQUID의 inductance 등 다양한 파라미터를 고려하여야 한다. 이러한 SQUID 회로의 복합적인 특성을 SQUID 에뮬레이터를 사용함으로써 FLL 회로를 손쉽게 설계할 수 있고, 또한 회로의 최적화도 쉽게 이를 수 있다. 또한 초전도에서 동작하는 SQUID 나 자기 차폐실이 없어도 FLL 회로 등을 개발할 수 있기 때문에 생체자기시스템의 개발 초기 단계에 널리 활용될 수 있다. 따라서 이 논문의 목적은 FLL을 포함한 SQUID 제어 회로를 SQUID 센서와 분리하기 위한 방법을 제안하는 것으로 자기적으로 coupling되어 있는 feedback 회로를 회로적으로 addition을 수행하게 함으로써 SQUID와 분리하여 회로의 동작 및 특성을 측정할 수 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.24-26
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• 2015

최근 많이 활용되고 있는 라즈베리파이에 기반한 임베디드 시스템을 구축함에 있어서 사용자는 회로에 대한 이해와 하드웨어 비용이라는 측면에서 어려움을 갖게 되는 경우가 많다. 본 논문에서는 이러한 시스템을 가상으로 테스트할 수 있는 솔루션을 제안하고자 한다. 개발된 프로그램은 사용자가 실제 회로를 구성하는 것과 같이 가상의 공간에서 모듈을 배치하고 모듈 간에 선을 연결하는 것으로 회로를 구성하고 동작을 테스트할 수 있다 프로그램은 회로편집기, 인터프리터, 시뮬레이터의 세 가지 요소로 구성되어 있으며 전체 9개의 모듈을 제공하고 있다. 각각의 모듈은 제조사에서 제공하는 데이터 시트와 제원을 바탕으로 실제 회로 테스트를 거쳐 추상화하는 작업을 수행하였다. 개발된 프로그램의 품질수준을 한층 끌어올린다면 비용절감과 학습, 교육 측면에서 유용하게 이용될 수 있으며, 전기물리엔진의 구현, 실제 보드로 포팅이 가능한 수준의 인터프리터, 시뮬레이션 로직의 일반화가 필요할 것으로 판단된다.