• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.263-266
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.29-34
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• 1999

In this paper, a current comparative frequency automatic tuning circuit for the CMOS gm-C bandpass filters are designed with the new architecture. And also, when the designed circuit is compared to the typical tuning circuit, the designed circuit has very simple architecture that is composed of the current comparator and charge pump and operating in 3V power supply. The proposed tuning circuit automatically compensates the difference between the operating current of the transconductor and the specified reference Current. Using CMOS 0.8um parameter a biquad gm-C bandpass filter with center frequency($f_\circ$=60MHz) is designed, and according to the transistor size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operation of the proposed current comparative frequency automatic tuning circuit is verified.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1604-1613
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• 2018

The paper presents the equivalent circuit of an induction machine (IM) model which includes fundamental stray load and iron losses. The corresponding equivalent resistances are introduced and modeled as variable with respect to the stator frequency and flux. Their computation does not require any tests apart from those imposed by international standards, nor does it involve IM constructional details. In addition, by the convenient positioning of these resistances within the proposed equivalent circuit, the order of the conventional IM model is preserved, thus restraining the inevitable increase of the computational complexity. In this way, a compromise is achieved between the complexity of the analyzed phenomena on the one hand and the model's practicability on the other. The proposed model has been experimentally verified using four IMs of different efficiency class and rotor cage material, all rated 1.5 kW. Besides enabling a quantitative insight into the impact of the stray load and iron losses on the operation of mains-supplied and vector-controlled IMs, the proposed model offers an opportunity to develop advanced vector control algorithms since vector control is based on the fundamental harmonic component of IM variables.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.798-804
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• 2003

In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.401-402
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• 2008

This paper presents an efficient architecture of unified transform and quantization circuit for H.264/JPEG CODEC. The proposed unified transform circuit shares adders required for all transform operations. The proposed unified quantization circuit uses four multipliers. Our transform circuit and quantization circuit consist of 33,711 gates and 9,650 gates respectively. The maximum operating frequency is 100MHz with 130nm standard cells.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.