• 마이크로전자및패키징학회지
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• 제22권3호
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• pp.9-17
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• 2015

After its inception in 1994, the Journal of the Microelectronics and Packaging Society has continued to make significant strides in the number and quality of publications within its field. The interest in the microelectronics and packaging research has become more critical as consumer electronic products continue its increasing trend towards thinner and lighter devices that tests the boundaries of electronic devices. This study utilizes social network analysis of all published literature in the Journal for the past 22 years. Using the keywords and abstracts available within each individual article, the publications within the Journal has focused on major topics covering (1) flip chip, (2) reliability, (3) Cu, (4) IMC (intermetallic compounds), and (5) thin film. Using the social network relationship between keywords within articles, flip chip was closely associated with reliability, BGA (ball grid array), contact resistance, electromigration in many of the published research works within the Journal. From the centrality analysis, it was found that flip chip, reliability, Cu, thin film, IMC, and RF (radio frequency) to have a high degree of centrality suggesting these key areas of research have relatively high connectivity with other research topics within the Journal and is central to many of the research fields within the micro-electronics and packaging area. The cohesiveness analysis showed research clustering of five major cohesive sub-groups and was mapped to better understand the major area of research within this field. Research within the field of micro-electronics and packaging converges many disciplines of science and engineering. The continued evolution within this field requires an understanding of the rapidly changing industry environment and the consumer needs.

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• 마이크로전자및패키징학회지
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• 제6권3호
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• pp.19-24
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• 1999

이동통신 부품용으로 이용되는 적층 칩 대역통과 필터를 설계, 제작하였으며 설계된 칩 필터의 크기는 4.5 $\times$ 4.4 $\times$ l.8[mm]이고 중심주파수 및 통과대역은 700[MHz]$\pm$15[MHz], 삽입손실은 3.0[dB]이하이다. 적층 칩 필터의 제조는 $BiNbO_4$에 CuO 0.06wt%, $V_2O_5$ 0.lwt%를 첨가한 조성을 이용하였으며 테이프 캐스팅 후 AE 전극을 스크린 프린팅하여 제작하였다. 제작된 칩 필터의 삽입손실과 중심주파수 및 통과대역은 2.58[dB]와 692.5$\pm$15[MHz]로서 중심주파수는 설계 결과보다 7.5[MHz] 낮았으나 그외의 특성은 설계 결과와 유사함을 볼 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.195-202
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• 2003

In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.30-30
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• 2007

현재 다양한 종류의 RF 통신 제품이 시장에 등장하면서 제품의 경쟁력 확보에 있어 소형화 정도가 중요한 이슈가 되고 있다. Passive Device는 RF Circuit을 제작할 때 많은 면적을 차지하고 있으며 이를 감소시키기 위해 여러 연구가 진행되고 있다. 가장 효과적인 방법으로 반도체 집적기술로 크기를 줄이는 방법이 있으나, 공정이 비싸고 제작 시간이 오래 걸려 제품개발 시간과 개발비용이 상승하게 된다. 반면에 SoP-L 공정은 PCB 제작에 이용되는 일반적인 재료와 공정을 사용하므로 개발 비용과 시간을 줄일 수 있다. SoP-L의 또 하나 장점은 다종 재료를 다층으로 구성할 수 있다는 점이다. 최근 chip-type의 Device를 PCB 기판 안에 내장하는 방법의 RF Circuit 소형화 연구가 많이 진행되고 있다. 본 연구에서는 SoP-L 공정으로 chip-type 수동소자를 PCB 기판 내에 함몰하여 수동소자회로를 구현, 분석하여 보았다. 수동소자회로는 880 MHz~960 MHz(GSM) 영역과 1.71 GHz~1.88 GHz(DCS) 영역을 나누는 Diplexer를 구성하였다. 1005 size의 chip 6개로 구현한 Diplexer를 표면실장과 함몰공정으로 제작하고 Network Analyzer로 측정하여 비교하였다. chip 표면실장으로 구현된 Diplexer는 GSM에서 최대 0.86 dB의 loss, DCS에서 최대 0.68 dB의 loss가 나타났다. 표면실장과 비교하였을 때 함몰공정의 Diplexer는 GSM 대역에서 약 0.5 dB의 추가 loss가 나타났으며 목표대역에서 0.6 GHz정도 내려갔다. 이 결과를 바탕으로 두 공정 간 차이점을 확인하고, 함몰공정으로 chip-type 수동소자를 사용하였을 때 고려해야 할 점을 분석하였다. 이를 바탕으로 SoP-L 함몰공정의 안정성을 높여서 이것을 이용한 회로의 소형화에 적용이 가능할 것으로 기대한다. 특히 능동소자의 DC Power Control에서 고용량의 수동소자를 이용할 때 집적도를 높일 수 있을 것이다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.55-60
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• 2001

RF MEMS is an exciting emerging technology that has great potential to develop TOC (Transceiver-on-Chip). Applications of the RF MEMS to wireless communications systems are presented. The ability of the RF MEMS technology to enhance the performance and to reduce the size of passive components, in particular, switches, inductors, and tunable capacitors, is addressed. A number of potential wireless system opportunities for the TOC are awaiting the maturation of the RF MEMS technology.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• 마이크로전자및패키징학회지
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• 제7권4호
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• pp.17-22
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• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.