• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.115-119
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• 2000

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.03a
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• pp.1-20
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• 2002

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.123-144
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• 2003

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.19-26
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• 2007

This study was focused on the feasibility of ultrasonic bonding of Au flip chip bumps for a practical complementary metal oxide semiconductor (CMOS) image sensor with electroplated Au substrate. The ultrasonic bonding was carried out with different bonding pressures and times after the atmospheric pressure plasma cleaning, and then the die shear test was performed to optimize the ultrasonic bonding parameters. The bonding pressure and time strongly affected the bonding strength of the bumps. The Au flip chip bumps were successfully bonded with the electroplated Au substrate at room temperature, and the bonding strength reached approximate 73 MPa under the optimum conditions.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.270-277
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• 2003

Thermal performance of flip chip bonding with Sn-3.5Ag solder ball was studied. The temperature distribution was measured with IR(InfraRed) camera of 25 urn resolution. The measurement shows that most of the samples had much higher maximum temperature than average temperature. With central heater and 2.5 (W), the difference between maximum and average temperature is over $80^{\circ}C$. The distribution was influenced by the location of heater, the distance from heater to flip chip bonding, and the passivation opening of solder bumps. To reduce the maximum temperature, the bigger passivation opening, the smaller chip size, and the closer location of heater to flip chip bumps are preferrable.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.247-251
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• 2002

In this paper the maximum current carrying capability of ACAs flip chip joint is investigated based on two failure mechanisms: (1) degradation of the interface between gold stud bumps and aluminum pads; and (2) ACA swelling between chips and substrates under high current stress. For the determination of the maximum allowable current, bias stressing was applied to ACAs flip chip joint. The current level at which current carrying capability is saturated is defined as the maximum allowable current. The degradation mechanism under high current stress was studied by in-situ monitoring of gold stud bump-aluminum pad ACA contact resistance and also ACA junction temperature at various current level. The cumulative failure distributions were used to predict the lifetime of ACAs flip chip joint under high current stressing. These experimental results can be used to better understand and to improve the current carrying capability of ACA flip chip joint.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.35-40
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• 2000

MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.