• 전기전자학회논문지
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• 제26권3호
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• pp.422-429
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• 2022

조도센서 칩은 아날로그 회로의 트리밍이나 디지털 레지스터의 초기 값을 셋팅하기 위해 소용량의 eFuse(electrical Fuse) OTP(One-Time Programmable) 메모리 IP(Intellectual Property)를 필요로 한다. 본 논문에서는 1.8V LV(Low-Voltage) 로직 소자를 사용하지 않고 3.3V MV(Medium Voltage) 소자만 사용하여 128비트 eFuse OTP IP를 설계하였다. 3.3V 단일 MOS 소자로 설계한 eFuse OTP IP는 1.8V LV 소자의 gate oxide 마스크, NMOS와 PMOS의 LDD implant 마스크에 해당되는 총 3개의 마스크에 해당되는 공정비용을 줄일 수 있다. 그리고 1.8V voltage regulator 회로가 필요하지 않으므로 조도센서 칩 사이즈를 줄일 수 있다. 또한 조도센서 칩의 패키지 핀 수를 줄이기 위해 프로그램 전압인 VPGM 전압을 웨이퍼 테스트 동안 VPGM 패드를 통해 인가하고 패키징 이후는 PMOS 파워 스위칭 회로를 통해 VDD 전압을 인가하므로 패키지 핀 수를 줄일 수 있다.

• 한국정밀공학회지
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• 제27권1호
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• pp.91-98
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• 2010

The increasing of power and processing speed and miniaturization of central processor unit (CPU) used in electronics equipment requires better performing thermal management systems. A typical thermal management package consists of thermal interfaces, heat dissipaters, and external cooling systems. There have been a number of experimental techniques and procedures for estimating thermal conductivity of thin, compressible thermal interface material (TIM). The TIM performance is affected by many factors and thus TIM should be evaluated under specified application conditions. In compact packaging of electronic equipment the chip is interfaced with a thin heat spreader. As the package is made thinner, the coupling between heat flow through TIM and that in the heat spreader becomes stronger. Thus, a TIM characterization system for considering the heat spreader effect is proposed and demonstrated in detail in this paper. The TIM test apparatus developed based on ASTM D-5470 standard for thermal interface resistance measurement of high performance TIM, including the precise measurement of changes in in-situ materials thickness. Thermal impedances are measured and compared for different directions of heat dissipation. The measurement of the TIM under the practical conditions can thus be used as the thermal criteria for the TIM selection.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.178-178
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• 2009

전자제품의 고속화, 고집적화, 고성능이 요구되어짐에 따라 IC's 성능 향상을 통해 패키징 기술의 소형화를 필요로 하고 있어 소재나 칩 부품을 이용해 커패시터나 저항을 구현하여 내장시키는 임베디드 패시브 기술에 대한 연구가 많이 진행되어 지고 있다. 본 연구에서는 3D 패키징이 가능한 flexible 소재에 능, 수동 소자를 내장하기 위한 다층 flexible 기판 공정 기술에 대한 연구를 수행하였다. 기판제작을 위해 flexible 소재에 미세 형성이 가능한 폴리머 필름을 접착하였고 flexible 위에 후막 저항체 패턴을 퍼|이스트를 이용하여 형성하였다. 또한, 능동소자 내장을 위해 test chip을 제작하여 플립칩 본더를 이용해 flexible 기판에 접합한 후에 bonding film을 이용한 build up 공정을 통해 via를 형성하고 무전해 도금 공정을 거쳐 전기적인 연결을 하였다. 위의 공정을 통해 앓고 가벼울 뿐만 아니라 자유롭게 구부러지는 특성을 갖고 있는 능, 수동 소자 내장형 flexible 기판의 변형에 따른 전기적 특성을 평가하였다.

• 한국전기전자재료학회논문지
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• 제23권12호
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• pp.919-923
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• 2010

Copper pillar tin bump (CPTB) was developed for high density chip interconnect technology. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM -1250 dry film photoresist (DFR), copper electroplating method and Sn electro-less plating method. Mechanical shear strength measurements were introduced to characterize the bonding process as a function of thermo-compression. Shear strength has maximum value with $330^{\circ}C$ and 500 N thenno-compression process. Through the simulation work, it was proved that when the copper pillar tin bump decreased in its size, it was largely affected by the copper oxidation.

• 한국정밀공학회지
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• 제31권10호
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• pp.873-879
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• 2014

UV curable adhesives with different acrylic functionalities were synthesized for temporary bonding and debonding process in 3D multi-chip packaging process. The aim is to study various factors which have an influence on UV curing. The properties and curing behaviors were investigated by gel fraction, peel strength, probe tack, and shear adhesion failure temperature. The results show that the properties and curing behaviors are dependent on not only acrylic functionalities of binders but also UV doses and coating thickness.

• 비파괴검사학회지
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• 제25권2호
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• pp.81-86
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• 2005

본 논문에서는 반도체 패키지 내부결함의 비파괴 정량평가를 위한 ESPI 기법을 이용한 시스템 및 검사기 법을 제안하고 있으며, 검사시스템은 ESPI 검사장치, 열변형유도장치, 단열챔버로 구성되어있다. 기존 초음파, X-ray 기반의 검사기법에 비하여 측정시간 및 검사방법이 용이하며, 결함의 정량검출이 가능하다는 장점이 있다. 검사결과에서 대부분의 결함이 열 방출이 많은 칩 주위에서 박리결함으로 나타났으며, 원인은 층간 접착강도의 약화와 열분배 설계에서 문제점인 것으로 사료된다.

• Journal of Welding and Joining
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• 제32권3호
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.1383-1388
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• 2015

Proportional integral derivative (PID) control is one of the conventional control strategies. Industrial PID control has many options, tools, and parameters for dealing with the wide spectrum of difficulties and opportunities in manufacturing plants. It has a simple control structure that is easy to understand and relatively easy to tune. Injection mold is warming up to the idea of cycling the tool surface temperature during the molding cycle rather than keeping it constant. This “heating and cooling” process has rapidly gained popularity abroad. However, it has discovered that raising the mold wall temperature above the resin’s glass-transition or crystalline melting temperature during the filling stage is followed by rapid cooling and improved product performance in applications from automotive to packaging to optics. In previous studies, optimization methods were mainly selected on the basis of the subjective experience. Appropriate techniques are necessary to optimize the cooling channels for the injection mold. In this study, a digital signal processor (DSP)-based PID control system is applied to injection molding machines. The main aim of this study is to optimize the control of the proposed structure, including a digital PID control method with a DSP chip in the injection molding machine.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집A
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• pp.90-95
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• 2001

Thermo-mechanical and flexural behavior of a wire-bond plastic ball grid array (WB-PBGA) are characterized by high sensitive $moir{\acute{e}}$ interferometry. $Moir{\acute{e}}$ fringe patterns are recorded and analyzed at several various bending loads and temperature steps. At the temperature higher that $100^{\circ}C$, the inelastic deformation in solder balls became more dominant. As a result the bending of the molding compound decreased while temperature increased. The strain results show that the solder ball located at the edge of the chip has largest shear strain by the thermal load while the maximum average shear strain by the bending moment occurs in the end solder. The results also show that $moir{\acute{e}}$ interferometry is a powerful and effective tool in experimental studies of electronic packaging.

• 센서학회지
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• 제14권3호
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• pp.137-143
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• 2005

Research in the field of biosensor has enormously increased over the recent years. The metal-oxide semiconductor field effect transistor (MOSFET) type protein sensor offers a lot of potential advantages such as small size and weight, the possibility of automatic packaging at wafer level, on-chip integration of biosensor arrays, and the label-free molecular detection. We fabricated MOSFET protein sensor and proposed the gold-black electrode as the gate metal to improve the response. The experimental results showed that the output voltage of MOSFET protein sensor was varied by concentration of albumin proteins and the gold-black gate increased the response up to maximum 13 % because it has the larger surface area than that of planar-gold gate. It means that the expanded gate allows a larger number of ligands on same area, and makes the more albumin proteins adsorbed on gate receptor.