• Transactions of the Korean Society of Machine Tool Engineers
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• v.18 no.1
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• pp.116-121
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• 2009

Thermosonic flip chip bonding is an important technology for the electronic packaging due to its simplicity, cost effectiveness and clean and dry process. Mechanical properties of the horn and the shank, such as the natural frequency and the amplitude, have a great effect on the bonding capability of the transverse flip chip bonding system. In this research, two kinds of study are performed. The first is the new design of the clamp and the second is the effect of tolerance parameters to the performance of the system. The clamp with a bent shape is newly designed to hold the nodal point of the flip chip. The second is the effect of the design parameters on the vibration amplitude and planarity at the end of the shank. The variation of the tolerance parameters changes the amplitude and the frequency of the vibration of the shank. They, in turn, have an effect on the quantity of the plastic deformation of the gold ball bump, which determined the quality of the flip chip bonding. The tolerance parameters that give the great effect on the amplitude of the shank are determined using Taguchi's method. Error of set-up angle, the length and diameter of horn and error of the length of the shank are determined to be the parameters that have peat effect on the amplitude of the system.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.9-15
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• 2018

This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.1-6
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• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.101-105
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• 2019

The adhesion reliability of the epoxy molding compound (EMC) and the printed circuit board (PCB) interface is critical to the quality and lifetime of the chip package since the EMC protects PCB from the external environment during the manufacturing, storage, and shipping processes. It is necessary to measure adhesion energy accurately to ensure product reliability by optimizing the manufacturing process during the development phase. This research deals with the measurement of EMC/PCB interfacial adhesion energy of chip package that has warpage induced by the coefficient of thermal expansion (CTE) mismatch. The double cantilever beam (DCB) test was conducted to measure adhesion energy, and the spring back force of specimens with warpage was compensated to calculate adhesion energy since the DCB test requires flat substrates. The result was verified by comparing the adhesion energy of flat chip packages come from the same manufacturing process.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.84-88
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• 2013

These days embedded technology may be the most significant development in the electronics industry. The study focused on the development of active device embedding using flexible printed circuit in view of process and materials. The authors fabricated 30um thickness Si chip without any crack, chipping defects with a dicing before grinding process. In order to embed chips into flexible PCB, the chip pads on a chip are connected to bonding pad on flexible PCB using an ACF film. After packaging, all sample were tested by the O/S test and carried out the reliability test. All samples passed environmental reliability test. In the future, this technology will be applied to the wearable electronics and flexible display in the variety of electronics product.

• International Journal of Internet, Broadcasting and Communication
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• v.7 no.2
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1979-1981
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• 2002

새로운 방식의 일체형 flexible sensor module을 제작하였다. MEMS공정을 이용하여 제작된이 센서 모듈은 배선기판은 물론 strain sensor 역시 임의의 곡면에 실장을 위해 자유로운 굽힘이 가능하도록 제작되었다. 실리콘웨이퍼에 구현된 piezoresistor 스트레인 센서는 release-etch 방법을 통해 웨이퍼로부터 분리되어, 폴리이미드를 기판으로 하는 Flexible Sensor Array Module로 완성되었다. 소자와 기판을 따로 제작한 후 조립하는 기존의 방식에 비해, 웨이퍼 위에서 flexible 기판을 형성하여 수율이 높고 사진공정의 정밀도를 그대로 보전한 기판과 센서 어레이의 패키징이 가능하였으며, 칩을 기판에 실장하기 위한 정밀한 조립공정도 불필요하였다. 폴리이미드 기판은 전기도금을 통해 회로를 구성하여 1단계 패키징 (die to chip carrier)과 2단계 패키징 (chip to substrate)을 웨이퍼 레벨에서 완성하였다. 마지막으로 불산 용액을 통해 희생층을 제거함으로서 웨이퍼로 부터 센서어레이 모듈을 분리 하였다.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.11a
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• pp.53-81
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• 2006

A COG(Chip on Glass) bonding process that is one of display packaging technology and bonds between driver IC chip and a glass panel using ACF(Anisotropic Conductive Film)has been investigated by using diode laser. This method is possible to raise cure temperature of ACF within one second and can reduce the total process time for COG bonding by a conventional method such as a hot plate. Also we can get good pressure mark on the surface of electrodes and higher bonding strength than that by convention method. Results show that laser COG bonding can give low pressure bonding and decrease a warpage of panel. We believe that it can be applied to fine pitch module.