• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.467-468
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• 2012

• Journal of Welding and Joining
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• v.30 no.6
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• pp.113-119
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• 2012

Ultrasonic bonding is the novel packaging method for flip-chip with high yield and low-temperature bonding. The bonding module is a core part of the bonding machine, which can transfer the ultrasonic energy into the bonding spot. In this paper, we propose topology optimization technique which can make new design of boding modules due to the constraints on resonance frequency and mode shapes. The designed bonding module using topology optimization was fabricated in order to evaluate the bonding performance and reliable operation during the continuous bonding process. The actual production models based on the proposed design satisfied the target frequency range and ultrasonic power. The bonding test was performed using flip-chip with lead-free Sn-based bumps, the results confirmed that the bonding strength was sufficient with the designed bonding modules. Also the performance degradation of the bonding module was not observed after the 300-hour continuous process with bonding conditions.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.53-60
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• 2003

CCD(Charge-Coupled Device) wafers, with a layer of micro lenses on top, usually are not passivated with dielectric films. Micro lenses, in general, are made of polymer material, which usually has a large affinity for particles generated in the various chip fabrication processes, most notably the wafer sawing for chip-dicing. The particles deposited on the micro lens layer either seriously attenuate or deflect the incoming light and often lead to CCD failure. In this study we introduce new type of saws which would significantly reduce the particle-related problems found in conventional type of saws. In the new saws, the positions and diverging angles of side and center nozzles have been optimized so as to flush the particles effectively. In addition, an independent nozzle is added for the sole purpose of flushing the generated particles. The test results show that, with the new saws. the ratio of the particle-related CCD chip failures has been dropped drastically from 9.1% to 0.63%.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.15-20
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• 2012

In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.67-72
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• 2001

An Effort has been made to more accurately analyze the flow in the chip cavity, particularly to model the flow through the openings in the leadframe and correctly treat the thermal boundary condition at the leadframe. The theoretical analysis of the flow has been done by using the Hele-Shaw approximation in each cavity separated by a leadframe. The cross-flow through the openings in the leadframe has been incorporated into the Hele-Shaw formulation as a mass source term. The optimization program based on the complex method integrated with flow analysis program has been successfully used to obtain the optimal filling conditions to avoid short shot.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.131-135
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• 2002

In this project, we have developed various techniques for subminiaturization, surface implementation, high frequency design, small-sizes SMD, performance test and applications of ultra small chip antenna, which is a core component for the personal communication systems. We also obtained base techniques for the next-generation ultra small chip antenna design and fabrication techniques for an internationally competitive subminiature ultra small chip antenna. Center frequency is 2442.5MHz(Type), return loss is -10dB max, VSWR is 2max, xy max gain is -2dB min, size is 0.05ccmax.