• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.2
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• pp.193-201
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• 2011

Recently, mechanical reliabilities including a drop test have been a hot issue. In this paper, solder balls with new components which are Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu-0.05N are introduced, and board level drop test for them are conducted under JEDEC standard in which the board with 15 flip chips is dropped as 1,500g acceleration during 0.5ms. The drop simulations are studied by using a implicit method in the ANSYS LS-DYNA, and modal analysis is made. Through both analyses, the solder balls with new components are evaluated under the drop. It is found that the maximum stress of each chip is occurred between the solder ball and the PCB, and the highest value among the maximum stresses in the chips is occurred on the chip nearest to fixed holes on the board in the drop tests and simulations.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.75-79
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• 2013

Demands for semiconductor devices are dramatically increasing, and advancements in fabrication technology are allowing a step-up in the number of devices per unit area. As a result, semiconductor devices require higher heat dissipation, and thus, cooling solutions have become important for guaranteeing their operational reliability. In particular, in chip-in-board packages, in which chips and passives are embedded in the substrates for efficient device layout, heat dissipation is of greater importance. In this study, a thermal model for layers of different materials has been proposed, and then, the heat transfer has been simulated by imposing a set of appropriate boundary conditions. Heat generation can be predicted based on the results, which will be utilized as practical data for actual package design.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.8
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• pp.8-13
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• 2009

LED BLU(Back Light Unit), based on MCPCB(Metal Core Printed Circuit Board) with anodizing oxide dielectric layer and improved thermal dissipation property, are presented. Reflecting cups were also formed on the surface of the MCPCB such that optical coupling between neighboring chips were minimized for improving the photon extraction efficiency. LED chips were directly attached on the MCPCB by using the COB (Chip On Board) scheme.

• Korean Journal of Computational Design and Engineering
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• v.9 no.4
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• pp.416-424
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• 2004

In this paper, the heat transfer analysis and thermal stress analysis of the PCB(Printed Circuit Board) equipped in electronic Packages are carried out for various may types of chips on the PCB. And two structural PCB models are used in the analyses. The electronic chips on the PCB usually emit heat and this heat generates the thermal stress around the chip. The thermal load due to the heat generation of chips on the PCB may cause the malfunction of the electronic packages such as a monitor. a computer etc. Hence, the PCB should be designed to withstand these thermal loads. In this paper, the heat transfer analysis and thermal stress analysis are executed for the PCB model with pins and the analysis results are compared with the results for the PCB model without pins. The analysis results show that the PCB model without pins is not good for the thermal stress analysis of PCB, even though these two models have similar heat transfer characteristics. The analysis results also show that the highest thermal stress occurs in the pin especially attached to the highest temperature chip, and the PCB constrained to the electronic package on the long side is structurally more stable than other cases. The analyses of the PCB are executed using the finite element analysis code, NISA.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• Journal of the Korean Wood Science and Technology
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• v.41 no.6
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• pp.490-496
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• 2013

The board using recycled wood waste chip tends to decrease in terms of physical and mechanical properties. The reasons are notably different shape of chips, components of used adhesive and impurity content, which bring the irregular quality and downgrading of board. More over, the board has higher emissivity of formaldehyde than regular board, because recycled chip contains adhesives that were used to make previous products. This low quality of products weakens the price and quality competitiveness, and it led to bringing the issue of problem in Korean board industry. For these reason, in this study, boards using byproducts of plywood were made to evaluate physical and mechanical properties according to manufacturing conditions. As a result, The board was consists of 4~16 mesh chips for core layer and veneer on both face and they were combined using EMDI, and its' bending strength was 57.7 $N/mm^2$ which is 215% higher than that of OSB (26.8 $N/mm^2$). Moreover, the emissivity of formaldehyde was 0.7 ppm, this board seems to substitute OSB for rated sheathing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.990-994
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• 2003

This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.155-161
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• 2018

A Si chip with the Cu/Au bumps of $100-{\mu}m$ diameter was flip-chip bonded using different anisotropic conductive adhesives (ACAs) onto the local stiffness-variant stretchable substrate consisting of polydimethylsiloxane (PDMS) and flexible printed circuit board (FPCB). The average contact resistances of the flip-chip joints processed with ACAs containing different conductive particles were evaluated and compared. The specimen, which was flip-chip bonded using the ACA with Au-coated polymer balls as conductive particles, exhibited a contact resistance of $43.2m{\Omega}$. The contact resistance of the Si chip, which was flip-chip processed with the ACA containing SnBi solder particles, was measured as $36.2m{\Omega}$, On the contrary, an electric open occurred for the sample bonded using the ACA with Ni particles, which was attributed to the formation of flip-chip joints without any entrapped Ni particles because of the least amount of Ni particles in the ACA.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.2
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• pp.9-15
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• 2024

The effect of the residual impurity on the prepreg surface on the wettability of encapsulant for chip on board package was analyzed with microstructure, compositions and chemical bonds using a scanning electron microscope and X-ray photoelectron spectroscopy. As a result, the contact angle of w/ residual impurity sample was measured to be 28° higher than that of w/o residual impurity sample, and the C-O bond was decreased to be 4% lower than that of w/o residual impurity sample. The surface energy of the prepreg decreased because the impurity ions, Na and F, generated by the manufacturing process and wet etching, reacted chemically with the C on the prepreg surface, forming C-F bonds and breaking the C-O bonds on the prepreg surface. Therefore, the wettability of the encapsulant was degraded because the contact angle between the encapsulant and the prepreg was increased.