• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Journal of Ocean Engineering and Technology
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• v.10 no.3
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• pp.162-167
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• 1996

This paper deals with an implementation method for the one chip microprocessor(8097)-based capacitance type wave recorder for a measuring real-time wave height. The system was developed to make it possible to real-time remote sensing the wave height by deploying the RS-232/422/485 communication methods. The system test results for the developed system such as linearity, system stability and robustness of the disturbance was also verified through the performance tests of the system. Furthermore, the system was developed after due consideration with connecting the public network such as satellite mobile communication system and LAN, through the deploying VLSI(Very Large Scale Integration) design techniques.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1724-1729
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• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature/humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the Electrochemical migration

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.4
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1229-1230
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• 2015

Monitoring of mechanical properties of tissues as well as direction/quantities of forces is considered as an essential way for disease diagnosis and haptic feedback systems. There are extensively increasing interests for measuring normal/shear force and touch feelings, especially for surgery systems. Highly sensitive and flexible tactile sensor is needed in palpation for detecting cancer cyst as well as real time pressure monitoring in minimally invasive surgery (MIS). Importantly, MEMS technique with miniaturized fabrication technique is essential for the on-chip integration with biopsy and biomedical grasper. Here, we propose the flexible tactile sensor with high sensitivity based on piezoresistive effect. We analyzed the sensitivity according to the pressure and directions and showed the ability of discrimination of the different materials surfaces, illustrating the feasibility of the flexible tactile sensor for biomedical grasper by mimicking human skin.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.175-181
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• 2005

SiOB is an essential part of slim optical pickup, where the silicon mirror, LD stand, silicon PD are integrated and LD is flip chip bonded. SiOB is fabricated with bulk micromachining. Especially the fabrication of silicon wafer with stepped concave areas has many extraordinary difficulties. As a matter of fact, experiences and knowledges are rare in the fabrication of the highly stepped silicon wafer. The difficulties occurring in the integration of PD and SiOB, and highly stepped patterning, and silicon mirror roughness and how-to-solve will be discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.727-731
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• 2005

Design and manufacturing process of a full color LED microdislay fabricated by standard CMOS technology and containing an array of aluminum / nanostructured porous silicon reverse biased light emitting Schottky diodes will be discussed. Being of a solid state construction, this microdisplays are cost-effective, thin and light in weight due to very simple device architecture. Its benefits include also super high resolution, wide viewing angles, fast response time and wide operating temperature range. The advantages of full integration of an LED-array and driving circuitry onto a Si-chip will be also discussed.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.3
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• pp.156-162
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• 2003

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.