• 대한금속재료학회지
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• 제48권6호
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• 전기학회논문지
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• 제57권12호
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• pp.2276-2280
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• 2008

In this paper, we present thermal dependancy of LED package element by changing temperature of MCPCB for design high efficiency LED lamp, and confirmed influence of LED chip against temperature with analysis of thermal resistance and thermal capacitance. As increasing temperature, WPOs were decreased from 25 to 22.5 [%] and optical power were also decreased. that is decreased reason of optical power that forward voltage was declined by decrease of energy bandgap. Therefore optical power by temperature of MCPCB should consider to design lamp for street light and security light. Moreover, compensation from declined optical efficiency is demanded when LED package is composed. Also, thermal resistances from chip to metal PCB were decreased from 12.18 to 10.8[$^{\circ}C/W$] by changing temperature. Among the thermal resistances, the thermal resistance form chip to die attachment was decreased from 2.87 to 2.5[$^{\circ}C/W$] and was decreased 0.72[$^{\circ}C/W$] in Heat Slug by chaning temperature. Therefore, because of thermal resistance gap in chip and heat slug, reliability and endurance of high power LED affect by increasing non-radiative recombination in chip from heat.

• 한국산업융합학회 논문집
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• 제7권4호
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• pp.325-330
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• 2004

The forces acting on the tool are an important aspect of maching. For those concerned with the manufacture of machine tools, a knowledge of the forces in needed for estimation of power reguirements and for the design of machine tool elements tool-holders and fixtures, adequately rigid and free from vibration. The force reguired to form the chip is dependent on the shear yield strength of the work material un der cutting conditions which are cutting speed, workpiece, feedrate, insert type. In this study, FG, ML, MP, MC, C, RT inserts were investigated in turning using SM45C, SCM4, SKD11, SUS316, materials. The diameter of materials was 60mm, 80mm, 110mm. This paper presents MP were lowest and SKD11 were largest of the workpiece in cutting forces.

• 전자공학회논문지B
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• 제33B권3호
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• pp.186-192
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• 1996

A modified learning rule is introduced for the implementation of feedforward artificial neural networks with on-chip learning circuitry using standard analog CMOS technology. Learning rule, is modified form the EBP (error back propagation) rule which is one of the well-known learning rules for the feedforward rtificial neural nets(FANNs). The employed MEBP ( modified EBP) rule is well - suited for the hardware implementation of FANNs with on-chip learning rule. As a ynapse circuit, a four-quadrant vector-product linear multiplier is employed, whose input/output signals are given with voltage units. Two $2{\times}2{\times}1$ FANNs are implemented with the learning circuitry. The implemented FANN circuits have been simulatied with learning test patterns using the PSPICE circuit simulator and their results show correct learning functions.

• 한국조명전기설비학회지:조명전기설비
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• 제3권2호
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• pp.63-68
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• 1989

정지형 전원(Static Power Supply) 설계를 위한 다중 PAM 인버터에 관하여 논한다. 인버터의 제어부는 원칩 마이크로 컴퓨터(One-chip Microcomputer)로 구성하여 간단히 제어신호를 얻었고, 종단 구성은 더블 브리지 인버터와 3상 3권선 변압기로 구성하였다. 출력 파형은 제어기와 변압기를 이용하여 1주기당 22 스텝의 전압레벨로 다중 PAM파형을 합성하였으며, 저역 여파기(Low Pass Filter)에 의해 정현파에 가까운 파형을 얻었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1536-1539
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• 1987

This paper describes the method to extract CIF(Caltech Intermediate Form) by the digital image processing techniques from the VLSI chip. It is possible to represent to the layout editing system. The resolution of the image is 512 512 and 12 bits.

• 전기학회논문지P
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• 제61권1호
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• pp.47-54
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• 2012

This paper presents implementation of SVPWM technique for three phase Voltage Source Inverter using FPGA. Software-based vector-control calculations much this drawback, in order to improve the hardware-vector-control tries. Without the need for additional software, vector control algorithm is designed to be modular SOPC, and DSP will reduce most of the operations. In this paper, the SVPWM that using HDL for the AC motor vector control algorithm level, and the dead time part and the speed control in order to controled a speed detector and designed in the form of modules. Then ALTERA corporation Cyclone III series EP3C16F484 can be verified by implemented.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.451-454
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• 2002

In this paper, studied on the one-chip design of low cost for the micro-stepping drive having 5-phase Pentagon Type winding. Micro-stepping method in order to eliminate effectively the resonant phenomena and to Increase the positional resolution. This paper proposed trapezoidal current wave- form for current control and provided design- method by using only one-chip of low cost. Therefore the drive will be simple and small size. Also the drive will have a lot of advantage at commercial business. Finally the above study has been implemented on the VHDL. Simulation has been performed to verify the PWM for micro-stepping drive.

• 센서학회지
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• 제8권6호
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• pp.469-475
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• 1999

공작기계의 자동화 고속화에 의해 절삭 작업은 향상되고 있지만 선삭시 발생하는 연속형 고속형칩은 작업능률을 저하시킴으로 AE센서를 이용한 절삭 실험을 통하여 절삭 조건에 따른 AE 신호의 특징을 분석하고 칩과 관련된 신호특성을 분석결과 칩 형상에 가장 중요한 요인이 되는 것은 AE진폭 신호와 AE 에너지 신호였음을 확인하였으며, AE진폭 신호와 AE에너지 신호를 통계적 처리한 결과 에너지신호 보다는 진폭 신호의 첨도값이 선삭시 절삭특성을 잘 나타내 주고 있었으며, 비절삭에너지를 이용하여 절삭성능을 종합적으로 평가하였다.

• 한국전기전자재료학회논문지
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• 제14권11호
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• pp.874-878
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• 2001

Solder bump was electroplated on wafer for flip chip application. The process is as follows. Ti/Cu were sputtered and thick PR was formed by several coating PR layer. Fine pitch vias were opened using via mask and then Cu stud and solder bump were electroplated. Finally solder bump was formed by reflow process. In this paper, we opened 40㎛ vias on 57㎛ thick PR layer and electroplated solder bump with 70㎛ height and 40㎛ diameter. After reflow process, we could form solder bump with 53㎛ height and 43㎛ diameter. In plating process, we improved the plating uniformity within 3% by using ring contact instead of conventional multi-point contact.