• Journal of the Microelectronics and Packaging Society
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• v.26 no.2
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• pp.31-43
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• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.55-64
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• 2012

Until now, Side Channel Attack has been known to be effective to crack decrypt key such as smart cards, electronic passports and e-ID card based on Chip. Combination of Masking and shuffling methods have been proposed practical countermeasure. Newly, S.Tillich suggests biased-mask using template attack(TA) to attack AES with masking and shuffling. However, an additional assumption that is acquired template information previously for masking value is necessary in order to apply this method. Moreover, this method needs to know exact time position of the target masking value for higher probability of success. In this paper, we suggest new practical method called Biasing Power Analysis(BPA) to find a secret key of AES based on masking-shuffling method. In BPA, we don't use time position and template information from masking value. Actually, we do experimental works of BPA attack to 128bit secret key of AES based on masking-shuffling method performed MSP430 Chip and we succeed in finding whole secret key. The results of this study will be utilized for next-generation ID cards to verify physical safety.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Journal of Welding and Joining
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• v.30 no.2
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• pp.65-69
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• 2012

Environmental and health concerns over the lead have led to investigation of the alternative Pb-free solders to replace commonly used Pb-Sn solders in microelectronic packaging application. The leading candidates for lead-free solder alloys are presently the near eutectic Sn-Ag-Cu alloys. Therefore, extensive studies on reliability related with the composition have been reported. However, the insufficient drop property of the near eutectic Sn-Ag-Cu alloys has demanded solder compositions of low Ag content. In addition, the solder interconnections in automobile applications like a smart box require significantly improved vibration resistance. Therefore, this study investigated the effect of alloying elements (Ag, Bi, In) on the vibration fatigue strength. The vibration fatigue was conducted in 10~1000Hz frequency and 20Grms. The interface of the as-soldered cross section close to the Cu pad indicated the intermetallic compound ($Cu_6Sn_5$) regardless of solder composition. The type and thickness of IMC was not significantly changed after the vibration test. It indicates that no thermal activities occurred significantly during vibration. Furthermore, as a function of alloying composition, the vibration crack path was investigated with a focus on the IMCs. Vibration crack was initiated from the fillet surface of the heel for QFP parts and from the plating layer of chip parts. Regardless of the solder composition, the crack during a vibration test was propagated as same as that during a thermal fatigue test.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.478-480
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• 2004

다이아몬드 톱날을 이용한 얇은 Si 웨이퍼의 기계적인 다이싱은 chipping, crack 등의 문제점을 발생시킨다. 또한 stacked die 나 multi-chip등과 같은 3D-WLP(wafer level package)에서 via를 생성하기 위해 현재 사용되는 화학적 etching은 공정속도가 느리고 제어가 힘들며, 공정이 복잡하다는 문제점을 가지고 있다. 이러한 문제점을 해결하기 위해 현재 연구되고 있는 분야가 레이저를 이용한 웨이퍼 다이싱 및 드릴링이다. 본 논문에서는 UV 레이저를 이용한 얇은 Si 웨이퍼 다이싱 및 드릴링 시스템에 대해 소개하고, 웨이퍼 다이싱 및 드릴링 실험결과를 바탕으로 적절한 레이저 및 공정 매개변수에 대해 설명한다.

• Journal of Applied Reliability
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• v.16 no.4
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• pp.347-355
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• 2016

Purpose: With the advance of miniaturization of electronic products, stacked packages of high density semiconductors are commonly used. Potential failure modes and mechanisms of stacked packages are identified. Methods: Failure modes and mechanisms of thin chip stacked packages are determined through the categorization and failure analysis: delamination, non-wet, crack, ESD, EMI and the process related damages. Results: Those failure modes are not easy to find and require excessive amount time and effort for analysis and subsequent improvement. Conclusion: In this study, a method of estimating the failure rate based on the strength measurement is suggested.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.220-223
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• 1996

Mechanical properties of Plasma-Enhanced Chemical Vapor Deposited (PECVD) silicon nitride thin film was studied to determine the feasibility of the film as a passivation layer over the aluminum bonding areas of integrated circuit chips. Ultimate strain of the films in thicknesses of about 5 k${\AA}$ was measured using four-point bending method. The ultimate strain of these films was constant at about 0.2% regardless of residual stress. Intrinsic and residual stresses of these films were measured and compared with thermal shock and cycling test results. Comparison of the results showed that more tensile films were more susceptible to crack- induced failure.

• Journal of Welding and Joining
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• v.20 no.5
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• pp.72-77
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• 2002

Flip-chip interconnection that uses solder bump is an essential technology to improve the performance of microelectronics which require higher working speed, higher density, and smaller size. In this paper, the shear strength of Cr/Cr-Cu/Cu UBM structure of the high-melting solder b01p and that of low-melting solder bump after aging is evaluated. Observe intermetallic compound and bump joint condition at the interface between solder and UBM by SEM and TEM. And analyze the shear load concentrated to bump applying finite element analysis. As a result of experiment, the maximum shear strength of Sn-97wt%Pb which was treated 900 hrs aging has been decreased as 25% and Sn-37wt%Pb sample has been decreased as 20%. By the aging process, the growth of $Cu_6Sn_5$ and $Cu_3Sn$ is ascertained. And the tendency of crack path movement that is interior of a solder to intermetallic compound interface is found.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.881-883
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• 2022

고객사에 납품하는 웨이퍼의 안정적인 공급을 위한 웨이퍼 엣지의 결함 검출 장비다. 본 연구에서는 OpenCV와 임베디드 시스템, 머신러닝, 전자 회로 그리고 센서/카메라 기술을 핵심 기술로 R&D 한다. 고객사에서 불량 웨이퍼 발생에 대응하기 위한 장비의 데이터를 생산하여 고객과의 신뢰도 향상 및 유지를 할 수 있다. 그리고 결함이 특정 공정 지점에서 발생하는지 탐색할 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12
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• pp.1142-1149
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• 2003

The strength and characteristics of the soldering interface of the power semiconductor chip in a power module has been firstly surveyed by the peel strength measurement method. A power module is combined with several power chips which generally has 30∼400$\textrm{mm}^2$ chip area to allow several tens or bigger amps in current rating, so that the traditional methods for interface characterization like shear test could not be applied to high power module. In this study power diode modules were fabricated by using lead-tin solder with 10${\times}$10$\textrm{mm}^2$ or 7${\times}$7$\textrm{mm}^2$ soldering interface. The peel strengths of soldered interfaces were measured and then the microscopic investigation on the fractured surfaces were followed. The peel test indicated that the crack propagated either through the bulk of the soft lead-tin solder which has 55-60 kgf/cm peel strength or along the interface between the solder and the plated nickel layer which has much lower 22 kgf/cm strength. This study showed that the peel test would be a useful method to quantify the solderability as well as to recognize which is the worst interface or the softest material in a power module with a large soldering area.