• Journal of Welding and Joining
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• v.26 no.1
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• pp.24-30
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• 2008

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2010.10a
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• pp.279-280
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• 2010

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.69-69
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• 2004

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2010.05a
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• pp.592-593
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• 2010

• Journal of Welding and Joining
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• v.29 no.1
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• pp.25-28
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• 2011

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.143-143
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• 1996

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.9-17
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• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.9-15
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• 2018

This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.