• Title/Summary/Keyword: Chip bonding

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미세 피치를 갖는 bare-chip 공정 및 시스템 개발

  • 강희석;정훈;조영준;김완수;강신일;심형섭
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2005.05a
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    • pp.79-83
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    • 2005
  • IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

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COG (Chip On Glass) Bonding Technology for Flat Panel Display Using Induction Heating Body in AC Magnetic Field (교류자기장에 의한 유도가열체를 이용한 평판 디스플레이용 COG (Chip On Glass) 접속기술)

  • Lee Yoon-Hee;Lee Kwang-Yong;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.4 s.37
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    • pp.315-321
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    • 2005
  • Chip-on-glass technology to attach IC chip directly on the glass substrate of flat panel display was studied by using induction heating body in AC magnetic field. With applying magnetic field of 230 Oe at 14 kHz, the temperature of an induction heating body made with Cu electrodeposited film of 5 mm${\times}$5 mm size and $600{\mu}m$ thickness reached to $250^{\circ}C$ within 60 seconds. However, the temperature of the glass substrate was maintained below $100^{\circ}C$ at a distance larger than 2 mm from the Cu induction heating body. COG bonding was successfully accomplished with reflow of Sn-3.5Ag solder bumps by applying magnetic field of 230 Oe at 14 kHz for 120 seconds to a Cu induction heating body of 5mm${\times}$5mm size and $600{\mu}m$ thickness.

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A Study on the Process Conditions of ACA( Anisotropic Conductance Adhesives) for COG ( Chip On Glass) (COG(Chip On Glass)를 위한 ACA (Anisotropic Conductive Adhesives) 공정 조건에 관한 연구)

  • Han, Jeong-In
    • Korean Journal of Materials Research
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    • v.5 no.8
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    • pp.929-935
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    • 1995
  • In order to develop COG (Chip On Glass) technology for LCD module interconnecting the driver IC to Al pad electrode on the glass substrate, Anisotropic Conductive Adhesive(ACA) process, the most promising one among COG technologies, was investigated. ACA process was carried out by two steps, dispensing of ACA resin in the bonding area and curing by W radiation. Load on the chip was ranged from 2.0 to 15kg and the chip was heated at about 12$0^{\circ}C$. In resin, the density of conductive particles coated with Au or Ni at the surface were 500, 1000, 2000 and 4000 particles/$\textrm{mm}^2$, and the diameter of particles were 5, 7 and 12${\mu}{\textrm}{m}$. As a result of the experiments, ACA process using ACA particle of diameter and density of 5${\mu}{\textrm}{m}$ and 4000 particles/$\textrm{mm}^2$ respectively shows optimum characteristic with the stabilzed bonding properties and contact resistance.

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The Characteristics of Thermal Resistance for Fluxless Eutectic Die Bonding in High Power LED Package (Fluxless eutectic die bonding을 적용한 high power LED 패키지의 열저항 특성)

  • Shin, Sang-Hyun;Choi, Sang-Hyun;Kim, Hyun-Ho;Lee, Young-Gi;Choi, Suk-Moon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.303-304
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    • 2005
  • In this paper, we report a fluxless eutectic die bonding process which uses 80Au-20Sn eutectic alloy. The chip LEDs are picked and placed on silicon substrate wafers. The bonding process temperatures and force are $305\sim345^{\circ}C$ and 10$\sim$100gf, respectively. The bonding process was performed on graphite heater with nitrogen atmosphere. The quality of bonding are evaluated by shear test and thermal resistance. Results of fluxless eutectic die bonding show that shear strength is Max. 3.85kgf at 345$^{\circ}C$ /100gf and thermal resistance of junction to die bonding is Min. 3.09K/W at 325$^{\circ}C$/100gf.

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Leadframe Feeder Heat Rail Design and Verification (Leadframe Feeder Heat Rail의 설계와 검증)

  • Kim, Won-Jong;Hwang, Eun-Ha
    • Journal of the Korean Society of Industry Convergence
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    • v.15 no.1
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    • pp.37-42
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    • 2012
  • Trends in semiconductor equipment industry are to reduce the cost of producing semiconductor, semiconductor process development, facility development, and the minimum investment in terms of cost and quality. Semiconductor equipments are being considered to review and development is proceeding at the same time. In the first part of the semiconductor assembly process, in which the importance of die bonding process is emerging, a wide leadframe type die bonding machine is demanded for productivity. Die bonding machine was designed through experiments and by trial and error. It costs a lot of time and financial burden. The purpose of this study is to solve these problems by using the CAE tool 3G. By using finite element method, thermal analysis of die bonding machine to the various widths leadframe die bonder machine rail is performed for design.

Development of Repair FPC Bonder (리페어 FPC 본더 개발)

  • Ahn Jung-Woo;Seo Ji-Weon
    • Journal of the Semiconductor & Display Technology
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    • v.4 no.4 s.13
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    • pp.27-31
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    • 2005
  • This article contains the development of FPC bonder that used for repair or trial product. Nowadays, in FPO module process (including PDP) accept the thermo-compress bonding method when attach FPC(Flexible Printed Circuit Board), TCP(Tape Carrier Package) and COF(Chip on the FPC) by ACF(Anisotropic Conductive Film). This system consists of ACF attachment part, pre-bonding part, main bonding part, loading / unloading part. This composition is a stand-alone system, not an in-line system. Hereafter, this composition should be developing into in-line system in all area of FPD industry.

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Deep Learning-Based Defect Detection in Cu-Cu Bonding Processes

  • DaBin Na;JiMin Gu;JiMin Park;YunSeok Song;JiHun Moon;Sangyul Ha;SangJeen Hong
    • Journal of the Semiconductor & Display Technology
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    • v.23 no.2
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    • pp.135-142
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    • 2024
  • Cu-Cu bonding, one of the key technologies in advanced packaging, enhances semiconductor chip performance, miniaturization, and energy efficiency by facilitating rapid data transfer and low power consumption. However, the quality of the interface bonding can significantly impact overall bond quality, necessitating strategies to quickly detect and classify in-process defects. This study presents a methodology for detecting defects in wafer junction areas from Scanning Acoustic Microscopy images using a ResNet-50 based deep learning model. Additionally, the use of the defect map is proposed to rapidly inspect and categorize defects occurring during the Cu-Cu bonding process, thereby improving yield and productivity in semiconductor manufacturing.

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Warpage and Stress Simulation of Bonding Process-Induced Deformation for 3D Package Using TSV Technology (TSV 를 이용한 3 차원 적층 패키지의 본딩 공정에 의한 휨 현상 및 응력 해석)

  • Lee, Haeng-Soo;Kim, Kyoung-Ho;Choa, Sung-Hoon
    • Journal of the Korean Society for Precision Engineering
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    • v.29 no.5
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    • pp.563-571
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    • 2012
  • In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.

A Study on the Bonding Performance of COG Bonding Process (COG 본딩의 접합 특성에 관한 연구)

  • Choi, Young-Jae;Nam, Sung-Ho;Kim, Kyeong-Tae;Yang, Keun-Hyuk;Lee, Seok-Woo
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.7
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    • pp.28-35
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    • 2010
  • In the display industry, COG bonding method is being applied to production of LCD panels that are used for mobile phones and monitors, and is one of the mounting methods optimized to compete with the trend of ultra small, ultra thin and low cost of display. In COG bonding process, electrical characteristics such as contact resistance, insulation property, etc and mechanical characteristics such as bonding strength, etc depend on properties of conductive particles and epoxy resin along with ACF materials used for COG by manufacturers. As the properties of such materials have close relation to optimization of bonding conditions such as temperature, pressure, time, etc in COG bonding process, it is requested to carry out an in-depth study on characteristics of COG bonding, based on which development of bonding process equipment shall be processed. In this study were analyzed the characteristics of COG bonding process, performed the analysis and reliability evaluation on electrical and mechanical characteristics of COG bonding using ACF to find optimum bonding conditions for ACF, and performed the experiment on bonding characteristics regarding fine pitch to understand the affection on finer pitch in COG bonding. It was found that it is difficult to find optimum conditions because it is more difficult to perform alignment as the pitch becomes finer, but only if alignment has been made, it becomes similar to optimum conditions in general COG bonding regardless of pitch intervals.

Relationship between Contrast Ratio of Conductive Particle and Contact Resistance on COG Bonding using ACF (ACF를 이용한 COG 접합 공정에서 도전볼의 음영비와 접촉 저항과의 관계)

  • Jin, Songwan;Jeong, Young Hun;Choi, Eun Soo;Kim, Bosun;Yun, Won-Soo
    • Journal of the Korean Society for Precision Engineering
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    • v.31 no.9
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    • pp.831-838
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    • 2014
  • Chip on glass (COG) bonding using anisotropic conductive film (ACF) is a key technology to assemble a driver IC onto a LCD glass panel. In this paper, an experimental investigation was conducted to investigate the correlation between contact resistance and characteristics of image taken by machine vision based inspection system. The results show that the contact resistance was strongly influenced by the contrast ratio of conductive particle rather than the number of conductive particles. Also, number of conductive particles whose contrast ratio is below 0.75 is crucial for determining the quality of the assembled samples. On the other hand, in the result of high temperature high humidity storage test, the contrast ratio of samples was increased. However, in the case of open-circuit samples after temperature humidity storage test, the number of conductive particles whose contrast ratio is above 0.75 was more than that of the closed-circuit samples.