• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.384-393
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• 2013

In this paper, a design of planar microwave bias-tee using lumped elements was presented. The bias-tee is composed of 2 blocks; DC block and RF choke. For this design of the bias-tee, a wideband capacitor was used for DC block. For a RF choke, a series connection of inductors which have different SRFs is used for a RF choke. In the RF choke, a series connection of resistor and capacitor was added in shunt to eliminate a loss from a series resonance. The designed bias-tee was implemented by using 1608 SMT chip components. The fabricated bias-tee was measured using Anritsu 3680K fixture which enables to remove an effect of a connector. The fabricated bias-tee presented -15 dB of return loss and -1.5 dB insertion loss at 10 MHz~18 GHz.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.61-64
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• 2000

We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.946-951
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• 2000

In this paper, we showed the characteristic of transmission line with DCS (Defected Ground Structure), which is etched on the metallic ground plane. And we extracted the equivalent element value of DGS section. Effects of a lumped element placed on DGS section were investigated by employing DGS of dumbbell shape and parallel resonator with DGS. Chip type resistor, inductor, and capacitor were chosen as lumped elements for experiments. Experimental results show that the Q-factor and resonant frequency of the proposed DGS section can be controlled directly by using the external lumped element.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.490-492
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• 2010

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about $50{\Omega}$, was implemented using a 70nm 1-poly 3-metal DRAM process with a 1.5V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.

• Journal of Sensor Science and Technology
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• v.33 no.1
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• pp.56-61
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• 2024

The quality of the display can be managed by effectively managing the temperature generated by the panel during use. Conventional display panels rely on an external reference resistor for temperature monitoring. However, this approach is easily affected by external factors such as temperature variations from the driving circuit and chips. These variations reduce reliability, causing complicated mounting owing to the external chip, and cannot monitor the individual pixel temperatures. However, this issue can be simply and efficiently addressed by integrating temperature sensors during the display panel manufacturing process. In this study, we fabricated and analyzed a temperature sensor integrated into an a-IGZO (amorphous indium-gallium-zinc-oxide) TFT array that was to precisely monitor temperature and prevent the deterioration of OLED display pixels. The temperature sensor was positioned on top of the oxide TFT. Simultaneously, it worked as a light shield layer, contributing to the reliability of the oxide. The characteristics of the array with integrated temperature sensors were measured and analyzed while adjusting the temperature in real-time. By integrating a temperature sensor into the TFT array, monitoring the temperature of the display became easier and more accurate. This study could contribute to managing the lifetime of the display.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.376-383
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each subsystem, this partition will cause unwanted effects. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is used for the way of maintaining radiated emission, still specific user's guide doesn't give sufficient principle. In a view point of EMI, design principle of multi-CB using method will be analyzed by measurement. And design principle of noise mitigation will be provided. Generally interval of multi-CB is ${\lambda}/20$ ferrite bead. In this study, When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of EMI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.366-375
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each sub system, this partition will cause unwanted effects. In a circuital point of view, RCP partition has a bad influence upon signal integrity. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is usecl for the way of maintaining signal integrity, still specific user's guide doesn't give sufficient principle. In a view point of signal integrity, design principle of multi-CB using method will be analyzed by measurement and simulation. And design principle of noise mitigation will be provided. Generally interval of CB is ${\lambda}/20$ ferrite bead. In this study. When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement and simulation. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of signal integrity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.