• Journal of Communications and Networks
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• v.9 no.1
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• pp.50-55
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• 2007

We propose to apply chip interleaving and iterative detection to self-encoded multiple access (SEMA) communications. In SEMA, the spreading code is obtained from user bit information itself without using a pseudo noise code generator. The proposed scheme exploits the inherent diversity in self encoded spread spectrum signals. Chip interleaving not only increases the diversity gain, but also enhances the performance of iterative detection. We employ user-mask and interference cancellation to decouple self-encoded multiuser signals. This paper describes the proposed scheme and analyzes its performance. The analytical and simulation results show that the proposed system can achieve a 3 dB power gain and possess a diversity gain that can yield a significant performance improvement in both Rayleigh and multipath fading channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1186-1192
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• 2005

In this paper, we propose a novel channel estimation method based on pilot channel in a frequency interleaved multicarrier code division multiple access (MC-CDMA). Using the chip interleaving (CI) technique in the frequency domain make it possible to achieve higher frequency diversity gain than the system with conventional symbol interleaving. However, in CI-MC-CDMA systems, a pilot channel-based channel estimation (PCCE) cannot be applied because the orthogonality between pilot symbols and the data symbol is not maintained. The proposed method alters the system structure in order to maintain orthogonality between data and pilot channels over two consecutive subcarriers. Therefore, it can obtain accurate channel state information (CSI) in CI-MC-CDMA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.11
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• pp.1-7
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• 2004

We propose multistage parallel nulling (MPN) partial parallel interference cancellation (PPIC) receiver for downlink multiple-input multiple-output (MIMO) multicarrier (MC)-code division multiple access (CDMA) systems. Though the V-BLAST is a popular MIMO receiver, it shows error floor for multiuser downlink MIMO MC-CDMA systems. The proposed MPN-PPIC receiver does not produce error floor for multiuser case, and achieves substantial performance gains with multistage processing. For single user case, the proposed method also surpasses the V-BLAST receiver with multistage processing for MIMO MC-CDMA systems with chip level interleaving. The system performance of the proposed MPN-PPIC receiver is evaluated through computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.152-155
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• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.427-430
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• 2005

A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.450-456
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• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.56-64
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• 2017

In this paper, an advanced ZigBee (AZB) system for internet-of-things (IoT) applications is proposed which can support various data rates from 31.25 Kbps to 2 Mbps, and the implementation results of the AZB baseband processor are presented. Repetition coding for 32-chip direct-sequence spread spectrum (DSSS) symbol is applied for low rates under 250 Kbps to extend the coverage. Convolution coding, puncturing, and interleaving for non-DSSS symbol are performed for high rates from 500 Kbps to 2 Mbps for multi-media services. Simulation results show that the coverage increases at the rate of 51.8-77.3% for various environments compared with IEEE 802.15.4 ZigBee. AZB baseband processor was implemented in 180 nm CMOS process and total gate counts are 260K with the size of $5.8mm^2$.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.