• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.7
• /
• pp.103-110
• /
• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.14 no.6
• /
• pp.1515-1522
• /
• 1990

Ultra precision cutting should be satisfied with two conditions of Mirror Like and shape grade, and especially Mirror Like depends on surface roughness. In this study, in order to develop Mirror Cutting for Al alloy, this was done with edge form of single crystal diamond tool divided into R type and S type. Surface roughness machined by S type tool is more satisfactory than by R type tool, being the lowest value of 13.8nm. In addition, Mirror surface can reach above 90% of reflection rate by both R type and S type tool, but machined surface by R type tool has much more fine fracture portions rather than by S type tool. Even though feed rate decreases from 5.mu.m to 1.mu.m, surface roughness doesn't show improvement.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.2
• /
• pp.51-57
• /
• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• ETRI Journal
• /
• v.42 no.4
• /
• pp.480-490
• /
• 2020

More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.101-107
• /
• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.4
• /
• pp.91-95
• /
• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• International Journal of Precision Engineering and Manufacturing
• /
• v.2 no.2
• /
• pp.38-47
• /
• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.8
• /
• pp.940-945
• /
• 2008

In this paper, we have designed the Brick Transmit/Receive Module for K-band which can be applied to active phase array radar system. The proposed structure of T/R Module for K band is brick type for MCM(Multi Chip Module) form and the satisfaction of tile type T/R Module can apply to structure of cavity and main characteristic. The fabricated brick type T/R Module confirmed the main characteristic for electrical goal performance in test and this structure can be applied to active phase array radar.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.1
• /
• pp.88-95
• /
• 2004

Micro stepping method is adopted in order to eliminate effectively the resonant phenomena and to increase the positional resolution. Exist micro-step method by using Sinusoidal waveform, drive circuit is complex by using micro controller and ROM, it have fault on cost Increase. This paper proposed trapezoidal current wave form for simple control circuit and micro stepping method by using a low cost controller. This paper proposed method verify by using CPLD(EPM9320RC208-15) of low cost. This paper make experiment that comparison of exist method and proposed method. This paper obstruct a escape of motor by using high speed detect.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.63 no.1
• /
• pp.85-91
• /
• 2014

As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.